From 1983260e6f4cd8a30fb8535b873090ce23fd49e0 Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Sun, 10 Aug 2014 23:08:21 -0700
Subject: [PATCH] a few more fixes. some param lookups fail (here() in Alter
 blocks)

---
 rocket                          |  2 +-
 src/main/scala/RocketChip.scala | 13 +++++++------
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/rocket b/rocket
index 6beea1de..f0f84ed6 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit 6beea1debbdd8115f45d02318210df624e67e9f8
+Subproject commit f0f84ed6f953388a046c3296ccd0a3640ca6bd48
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 5bfa8698..d14436e1 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -109,10 +109,10 @@ class DefaultConfig extends ChiselConfig {
           case Entries => 62
           case NRAS => 2
           case MatchBits => site(PgIdxBits)
-          case Pages => ((1 max(log2Up(here(Entries))))+1)/2*2
+          case Pages => ((1 max(log2Up(site(Entries))))+1)/2*2 //TODO PARAMS no here?
           // control logic assumes 2 divides pages
           case OpaqueBits => log2Up(here(Entries))
-          case NBHT => 1 << log2Up(here(Entries)*2)
+          case NBHT => 1 << log2Up(site(Entries)*2) //TODO PARAMS no here?
         })
       //MemoryConstants
       case "CACHE_DATA_SIZE_IN_BYTES" => 1 << 6
@@ -132,9 +132,9 @@ class DefaultConfig extends ChiselConfig {
       case TileLinkL1Params => Alter({
           case LNMasters => site[Int]("NBANKS")
           case LNClients => site[Int]("NTILES")+1
-          case LNEndpoints => here(LNMasters) + here(LNClients)
+          case LNEndpoints => site[Int]("NBANKS") + site[Int]("NTILES")+1 // TODO PARAMS why broken?: site(LNMasters) +site(LNClients)
           case TLCoherence => site(Coherence)
-          case TLAddrBits => site[Int]("PADDR_BITS") - site[Int]("OFFSET_BITS")
+          case TLAddrBits => site(PAddrBits) - site[Int]("OFFSET_BITS")
           case TLMasterXactIdBits => log2Up(site[Int]("NL2_REL_XACTS")+site[Int]("NL2_ACQ_XACTS"))
           case TLClientXactIdBits => 2*log2Up(site[Int]("NMSHRS")*site[Int]("NTILES")+1)
           case TLDataBits => site[Int]("CACHE_DATA_SIZE_IN_BYTES")*8
@@ -348,9 +348,10 @@ class Top extends Module {
   val nTiles = params(NTiles)
   val io = new VLSITopIO
 
-  params.alter(params(TileLinkL1Params))
+  val tl: PartialFunction[Any,Any] = params(TileLinkL1Params) //TODO PARAMS can't lookup in map() below?
+  params.alter(tl)
   val resetSigs = Vec.fill(nTiles){Bool()}
-  val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))))
+  val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r)), tl))//TODO PARAMS above alter() is insufficient?
   val uncore = Module(new Uncore)
 
   for (i <- 0 until nTiles) {