riscv/rocket-chip
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tilelink2 broadcast: make it controlled via Config

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This commit is contained in:
Wesley W. Terpstra
2016-11-17 17:26:49 -08:00
parent f4ca5ea1f3
commit 179c93db42
8 changed files with 43 additions and 46 deletions
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3
src/main/scala/rocketchip/Configs.scala
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@ -32,7 +32,6 @@ class BasePlatformConfig extends Config(
case PeripheryBusArithmetic => true
// Note that PLIC asserts that this is > 0.
case IncludeJtagDTM => false
case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
case ExtMem => AXIMasterConfig(0x80000000L, 0x10000000L, 8, 4)
case ExtBus => AXIMasterConfig(0x60000000L, 0x20000000L, 8, 4)
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
@ -63,7 +62,7 @@ class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
class WithNMemoryChannels(n: Int) extends Config(
(pname,site,here) => pname match {
case NMemoryChannels => Dump("N_MEM_CHANNELS", n)
case BankedL2Config => site(BankedL2Config).copy(nMemoryChannels = n)
case _ => throw new CDEMatchError
}
)