diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index d5a1ddec..88aae737 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -19,12 +19,25 @@ case class TLBusConfig(beatBytes: Int) case object CBusConfig extends Field[TLBusConfig] case object L1toL2Config extends Field[TLBusConfig] -/** Number of memory channels */ -case object NMemoryChannels extends Field[Int] -/** Number of banks per memory channel */ -case object NBanksPerMemoryChannel extends Field[Int] -/** Number of tracker per bank */ -case object NTrackersPerBank extends Field[Int] +/** L2 Broadcast Hub configuration */ +case class BroadcastConfig( + nTrackers: Int = 4, + bufferless: Boolean = false) +case object BroadcastConfig extends Field[BroadcastConfig] + +/** L2 memory subsystem configuration */ +case class BankedL2Config( + nMemoryChannels: Int = 1, + nBanksPerChannel: Int = 1, + coherenceManager: (Int, Parameters) => (TLInwardNode, TLOutwardNode) = { case (lineBytes, p) => + val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig) + val bh = LazyModule(new TLBroadcast(lineBytes, nTrackers, bufferless)) + (bh.node, bh.node) + }) { + val nBanks = nMemoryChannels*nBanksPerChannel +} +case object BankedL2Config extends Field[BankedL2Config] + /** The file to read the BootROM contents from */ case object BootROMFile extends Field[String] @@ -32,12 +45,10 @@ trait HasCoreplexParameters { implicit val p: Parameters lazy val cbusConfig = p(CBusConfig) lazy val l1tol2Config = p(L1toL2Config) - lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel) lazy val globalAddrMap = p(rocketchip.GlobalAddrMap) lazy val nTiles = p(uncore.devices.NTiles) - lazy val nMemChannels = p(NMemoryChannels) lazy val hasSupervisor = p(rocket.UseVM) - lazy val nTrackersPerBank = p(NTrackersPerBank) + lazy val l2Config = p(BankedL2Config) } case class CoreplexParameters(implicit val p: Parameters) extends HasCoreplexParameters @@ -99,19 +110,17 @@ trait CoreplexNetworkModule extends HasCoreplexParameters { trait BankedL2CoherenceManagers extends CoreplexNetwork { val module: BankedL2CoherenceManagersModule - require (isPow2(nBanksPerMemChannel)) + require (isPow2(l2Config.nBanksPerChannel)) require (isPow2(l1tol2_lineBytes)) - def l2ManagerFactory(): (TLInwardNode, TLOutwardNode) - - val mem = Seq.fill(nMemChannels) { + val mem = Seq.fill(l2Config.nMemoryChannels) { val bankBar = LazyModule(new TLXbar) val output = TLOutputNode() output := bankBar.node - val mask = ~BigInt((nBanksPerMemChannel-1) * l1tol2_lineBytes) - for (i <- 0 until nBanksPerMemChannel) { - val (in, out) = l2ManagerFactory() + val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes) + for (i <- 0 until l2Config.nBanksPerChannel) { + val (in, out) = l2Config.coherenceManager(l1tol2_lineBytes, p) in := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(l1tol2.node) bankBar.node := out } @@ -123,7 +132,7 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork { trait BankedL2CoherenceManagersBundle extends CoreplexNetworkBundle { val outer: BankedL2CoherenceManagers - require (nMemChannels <= 1, "Seq in Chisel Bundle needed to support > 1") // !!! + require (l2Config.nMemoryChannels <= 1, "Seq in Chisel Bundle needed to support > 1") // !!! val mem = outer.mem.map(_.bundleOut).toList.headOption // .headOption should be removed !!! } diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index 15bc225e..ea40693f 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -6,6 +6,7 @@ import Chisel._ import junctions._ import diplomacy._ import uncore.tilelink._ +import uncore.tilelink2._ import uncore.coherence._ import uncore.agents._ import uncore.devices._ @@ -100,7 +101,7 @@ class BaseCoreplexConfig extends Config ( coherencePolicy = ( if (useMEI) new MEICoherence(site(L2DirectoryRepresentation)) else new MESICoherence(site(L2DirectoryRepresentation))), - nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */, + nManagers = site(BankedL2Config).nBanks + 1 /* MMIO */, nCachingClients = 1, nCachelessClients = 1, maxClientXacts = max_int( @@ -114,10 +115,9 @@ class BaseCoreplexConfig extends Config ( dataBits = site(CacheBlockBytes)*8) } case BootROMFile => "./bootrom/bootrom.img" - case BufferlessBroadcast => false case NTiles => 1 - case NBanksPerMemoryChannel => Knob("NBANKS_PER_MEM_CHANNEL") - case NTrackersPerBank => Knob("NTRACKERS_PER_BANK") + case BroadcastConfig => BroadcastConfig() + case BankedL2Config => BankedL2Config() case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64) case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes)) case EnableL2Logging => false @@ -165,11 +165,11 @@ class WithL2Cache extends Config( case "L2Bank" => { case NSets => (((here[Int]("L2_CAPACITY_IN_KB")*1024) / site(CacheBlockBytes)) / - (site(NBanksPerMemoryChannel)*site(NMemoryChannels))) / + (site(BankedL2Config).nBanks)) / site(NWays) case NWays => Knob("L2_WAYS") case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat - case CacheIdBits => log2Ceil(site(NMemoryChannels) * site(NBanksPerMemoryChannel)) + case CacheIdBits => log2Ceil(site(BankedL2Config).nBanks) case SplitMetadata => Knob("L2_SPLIT_METADATA") }: PartialFunction[Any,Any] case NAcquireTransactors => 2 @@ -183,7 +183,7 @@ class WithL2Cache extends Config( class WithBufferlessBroadcastHub extends Config( (pname, site, here) => pname match { - case BufferlessBroadcast => true + case BroadcastConfig => site(BroadcastConfig).copy(bufferless = true) }) /** @@ -199,6 +199,13 @@ class WithBufferlessBroadcastHub extends Config( * DO NOT use this configuration. */ class WithStatelessBridge extends Config ( + topDefinitions = { (pname,site,here) => pname match { + case BankedL2Config => site(BankedL2Config).copy(coherenceManager = { case (_, _) => + val pass = LazyModule(new TLBuffer(0)) + (pass.node, pass.node) + }) + case _ => throw new CDEMatchError + }}, knobValues = { case "L1D_MSHRS" => 0 case _ => throw new CDEMatchError diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala index 3ef5ef27..a557dadf 100644 --- a/src/main/scala/coreplex/Coreplex.scala +++ b/src/main/scala/coreplex/Coreplex.scala @@ -10,20 +10,9 @@ import uncore.util._ import util._ import rocket._ -/** Should the broadcast hub have no buffers */ -case object BufferlessBroadcast extends Field[Boolean] - -trait BroadcastL2 extends BankedL2CoherenceManagers { - def l2ManagerFactory() = { - val bh = LazyModule(new TLBroadcast(l1tol2_lineBytes, nTrackersPerBank, p(BufferlessBroadcast))) - (bh.node, bh.node) - } -} - ///// class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex - with BroadcastL2 with CoreplexRISCVPlatform with RocketPlex { override lazy val module = new DefaultCoreplexModule(this, () => new DefaultCoreplexBundle(this)) @@ -119,7 +108,6 @@ trait AsyncConnectionModule { } class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex - with BroadcastL2 with AsyncConnection { override lazy val module = new MultiClockCoreplexModule(this, () => new MultiClockCoreplexBundle(this)) } diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala index a0645e01..66891edd 100644 --- a/src/main/scala/groundtest/Configs.scala +++ b/src/main/scala/groundtest/Configs.scala @@ -79,7 +79,7 @@ class WithGroundTest extends Config( coherencePolicy = ( if (useMEI) new MEICoherence(site(L2DirectoryRepresentation)) else new MESICoherence(site(L2DirectoryRepresentation))), - nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1, + nManagers = site(BankedL2Config).nBanks + 1, nCachingClients = 1, nCachelessClients = 1, maxClientXacts = ((site(DCacheKey).nMSHRs + 1) +: @@ -90,8 +90,6 @@ class WithGroundTest extends Config( dataBeats = dataBeats, dataBits = site(CacheBlockBytes)*8) } - case BuildExampleTop => - (p: Parameters) => LazyModule(new ExampleTopWithTestRAM(new GroundTestCoreplex()(_))(p)) case FPUKey => None case UseAtomics => false case UseCompressed => false diff --git a/src/main/scala/groundtest/Coreplex.scala b/src/main/scala/groundtest/Coreplex.scala index f1358cbc..fd94eb17 100644 --- a/src/main/scala/groundtest/Coreplex.scala +++ b/src/main/scala/groundtest/Coreplex.scala @@ -9,8 +9,7 @@ import uncore.tilelink2._ import rocket.TileId import uncore.tilelink.TLId -class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex - with BroadcastL2 { +class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex { val tiles = List.tabulate(p(NTiles)) { i => LazyModule(new GroundTestTile()(p.alterPartial({ case TLId => "L1toL2" diff --git a/src/main/scala/rocketchip/Configs.scala b/src/main/scala/rocketchip/Configs.scala index 5c94cd42..848a2941 100644 --- a/src/main/scala/rocketchip/Configs.scala +++ b/src/main/scala/rocketchip/Configs.scala @@ -32,7 +32,6 @@ class BasePlatformConfig extends Config( case PeripheryBusArithmetic => true // Note that PLIC asserts that this is > 0. case IncludeJtagDTM => false - case NMemoryChannels => Dump("N_MEM_CHANNELS", 1) case ExtMem => AXIMasterConfig(0x80000000L, 0x10000000L, 8, 4) case ExtBus => AXIMasterConfig(0x60000000L, 0x20000000L, 8, 4) case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock @@ -63,7 +62,7 @@ class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config) class WithNMemoryChannels(n: Int) extends Config( (pname,site,here) => pname match { - case NMemoryChannels => Dump("N_MEM_CHANNELS", n) + case BankedL2Config => site(BankedL2Config).copy(nMemoryChannels = n) case _ => throw new CDEMatchError } ) diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala index 81a1fde7..681c7f66 100644 --- a/src/main/scala/rocketchip/Periphery.scala +++ b/src/main/scala/rocketchip/Periphery.scala @@ -36,7 +36,6 @@ case object SOCBusConfig extends Field[TLBusConfig] /** Utility trait for quick access to some relevant parameters */ trait HasPeripheryParameters { implicit val p: Parameters - lazy val nMemChannels = p(NMemoryChannels) lazy val peripheryBusConfig = p(PeripheryBusConfig) lazy val socBusConfig = p(SOCBusConfig) lazy val cacheBlockBytes = p(CacheBlockBytes) diff --git a/src/main/scala/rocketchip/TestHarness.scala b/src/main/scala/rocketchip/TestHarness.scala index 8ac27c61..363ed0f8 100644 --- a/src/main/scala/rocketchip/TestHarness.scala +++ b/src/main/scala/rocketchip/TestHarness.scala @@ -9,8 +9,6 @@ import diplomacy._ import coreplex._ import uncore.axi4._ -case object BuildExampleTop extends Field[Parameters => ExampleTop[coreplex.BaseCoreplex]] - class TestHarness(q: Parameters) extends Module { val io = new Bundle { val success = Bool(OUTPUT)