tilelink2 broadcast: make it controlled via Config

src/main/scala/rocketchip/Configs.scala

@@ -32,7 +32,6 @@ class BasePlatformConfig extends Config(
         case PeripheryBusArithmetic => true
         // Note that PLIC asserts that this is > 0.
         case IncludeJtagDTM => false
-        case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
         case ExtMem => AXIMasterConfig(0x80000000L, 0x10000000L, 8, 4)
         case ExtBus => AXIMasterConfig(0x60000000L, 0x20000000L, 8, 4)
         case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
@@ -63,7 +62,7 @@ class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
 
 class WithNMemoryChannels(n: Int) extends Config(
   (pname,site,here) => pname match {
-    case NMemoryChannels => Dump("N_MEM_CHANNELS", n)
+    case BankedL2Config => site(BankedL2Config).copy(nMemoryChannels = n)
     case _ => throw new CDEMatchError
   }
 )

src/main/scala/rocketchip/Periphery.scala

@@ -36,7 +36,6 @@ case object SOCBusConfig extends Field[TLBusConfig]
 /** Utility trait for quick access to some relevant parameters */
 trait HasPeripheryParameters {
   implicit val p: Parameters
-  lazy val nMemChannels = p(NMemoryChannels)
   lazy val peripheryBusConfig = p(PeripheryBusConfig)
   lazy val socBusConfig = p(SOCBusConfig)
   lazy val cacheBlockBytes = p(CacheBlockBytes)

src/main/scala/rocketchip/TestHarness.scala

@@ -9,8 +9,6 @@ import diplomacy._
 import coreplex._
 import uncore.axi4._
 
-case object BuildExampleTop extends Field[Parameters => ExampleTop[coreplex.BaseCoreplex]]
-
 class TestHarness(q: Parameters) extends Module {
   val io = new Bundle {
     val success = Bool(OUTPUT)