riscv/rocket-chip
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tilelink2 broadcast: make it controlled via Config

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This commit is contained in:
Wesley W. Terpstra
2016-11-17 17:26:49 -08:00
parent f4ca5ea1f3
commit 179c93db42
8 changed files with 43 additions and 46 deletions
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43
src/main/scala/coreplex/BaseCoreplex.scala
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@ -19,12 +19,25 @@ case class TLBusConfig(beatBytes: Int)
case object CBusConfig extends Field[TLBusConfig]
case object L1toL2Config extends Field[TLBusConfig]
/** Number of memory channels */
case object NMemoryChannels extends Field[Int]
/** Number of banks per memory channel */
case object NBanksPerMemoryChannel extends Field[Int]
/** Number of tracker per bank */
case object NTrackersPerBank extends Field[Int]
/** L2 Broadcast Hub configuration */
case class BroadcastConfig(
nTrackers: Int = 4,
bufferless: Boolean = false)
case object BroadcastConfig extends Field[BroadcastConfig]
/** L2 memory subsystem configuration */
case class BankedL2Config(
nMemoryChannels: Int = 1,
nBanksPerChannel: Int = 1,
coherenceManager: (Int, Parameters) => (TLInwardNode, TLOutwardNode) = { case (lineBytes, p) =>
val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig)
val bh = LazyModule(new TLBroadcast(lineBytes, nTrackers, bufferless))
(bh.node, bh.node)
}) {
val nBanks = nMemoryChannels*nBanksPerChannel
}
case object BankedL2Config extends Field[BankedL2Config]
/** The file to read the BootROM contents from */
case object BootROMFile extends Field[String]
@ -32,12 +45,10 @@ trait HasCoreplexParameters {
implicit val p: Parameters
lazy val cbusConfig = p(CBusConfig)
lazy val l1tol2Config = p(L1toL2Config)
lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
lazy val globalAddrMap = p(rocketchip.GlobalAddrMap)
lazy val nTiles = p(uncore.devices.NTiles)
lazy val nMemChannels = p(NMemoryChannels)
lazy val hasSupervisor = p(rocket.UseVM)
lazy val nTrackersPerBank = p(NTrackersPerBank)
lazy val l2Config = p(BankedL2Config)
}
case class CoreplexParameters(implicit val p: Parameters) extends HasCoreplexParameters
@ -99,19 +110,17 @@ trait CoreplexNetworkModule extends HasCoreplexParameters {
trait BankedL2CoherenceManagers extends CoreplexNetwork {
val module: BankedL2CoherenceManagersModule
require (isPow2(nBanksPerMemChannel))
require (isPow2(l2Config.nBanksPerChannel))
require (isPow2(l1tol2_lineBytes))
def l2ManagerFactory(): (TLInwardNode, TLOutwardNode)
val mem = Seq.fill(nMemChannels) {
val mem = Seq.fill(l2Config.nMemoryChannels) {
val bankBar = LazyModule(new TLXbar)
val output = TLOutputNode()
output := bankBar.node
val mask = ~BigInt((nBanksPerMemChannel-1) * l1tol2_lineBytes)
for (i <- 0 until nBanksPerMemChannel) {
val (in, out) = l2ManagerFactory()
val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes)
for (i <- 0 until l2Config.nBanksPerChannel) {
val (in, out) = l2Config.coherenceManager(l1tol2_lineBytes, p)
in := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(l1tol2.node)
bankBar.node := out
}
@ -123,7 +132,7 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
trait BankedL2CoherenceManagersBundle extends CoreplexNetworkBundle {
val outer: BankedL2CoherenceManagers
require (nMemChannels <= 1, "Seq in Chisel Bundle needed to support > 1") // !!!
require (l2Config.nMemoryChannels <= 1, "Seq in Chisel Bundle needed to support > 1") // !!!
val mem = outer.mem.map(_.bundleOut).toList.headOption // .headOption should be removed !!!
}