From 166df221ad2d910e25c0f9173ffc3ba261b6c81a Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 6 Oct 2015 18:14:51 -0700 Subject: [PATCH] added HasAddrMapParameters --- junctions/src/main/scala/addrmap.scala | 27 ++++++++++++++++++++++++ junctions/src/main/scala/memserdes.scala | 9 -------- junctions/src/main/scala/nasti.scala | 6 ++---- 3 files changed, 29 insertions(+), 13 deletions(-) diff --git a/junctions/src/main/scala/addrmap.scala b/junctions/src/main/scala/addrmap.scala index f37111c9..8e6dea4e 100644 --- a/junctions/src/main/scala/addrmap.scala +++ b/junctions/src/main/scala/addrmap.scala @@ -5,6 +5,33 @@ package junctions import Chisel._ import scala.collection.mutable.HashMap +case object PAddrBits extends Field[Int] +case object VAddrBits extends Field[Int] +case object PgIdxBits extends Field[Int] +case object PgLevels extends Field[Int] +case object PgLevelBits extends Field[Int] +case object ASIdBits extends Field[Int] +case object PPNBits extends Field[Int] +case object VPNBits extends Field[Int] + +case object GlobalAddrMap extends Field[AddrMap] +case object MMIOBase extends Field[BigInt] + +trait HasAddrMapParameters { + implicit val p: Parameters + + val paddrBits = p(PAddrBits) + val vaddrBits = p(VAddrBits) + val pgIdxBits = p(PgIdxBits) + val ppnBits = p(PPNBits) + val vpnBits = p(VPNBits) + val pgLevels = p(PgLevels) + val pgLevelBits = p(PgLevelBits) + val asIdBits = p(ASIdBits) + + val addrMap = new AddrHashMap(p(GlobalAddrMap)) +} + abstract class MemRegion { def size: BigInt } case class MemSize(size: BigInt, prot: Int) extends MemRegion diff --git a/junctions/src/main/scala/memserdes.scala b/junctions/src/main/scala/memserdes.scala index a439c8a9..2fc8ace1 100644 --- a/junctions/src/main/scala/memserdes.scala +++ b/junctions/src/main/scala/memserdes.scala @@ -4,15 +4,6 @@ package junctions import Chisel._ import scala.math._ -case object PAddrBits extends Field[Int] -case object VAddrBits extends Field[Int] -case object PgIdxBits extends Field[Int] -case object PgLevels extends Field[Int] -case object PgLevelBits extends Field[Int] -case object ASIdBits extends Field[Int] -case object PPNBits extends Field[Int] -case object VPNBits extends Field[Int] - case object MIFAddrBits extends Field[Int] case object MIFDataBits extends Field[Int] case object MIFTagBits extends Field[Int] diff --git a/junctions/src/main/scala/nasti.scala b/junctions/src/main/scala/nasti.scala index 32e25228..f57ff9fc 100644 --- a/junctions/src/main/scala/nasti.scala +++ b/junctions/src/main/scala/nasti.scala @@ -6,8 +6,6 @@ import scala.math.max import scala.collection.mutable.ArraySeq case object NastiKey extends Field[NastiParameters] -case object NastiAddrMap extends Field[AddrMap] -case object MMIOBase extends Field[BigInt] case class NastiParameters(dataBits: Int, addrBits: Int, idBits: Int) @@ -571,9 +569,9 @@ class NastiRecursiveInterconnect( } } -class NastiTopInterconnect(val nMasters: Int, val nSlaves: Int) +class NastiTopInterconnect(val nMasters: Int, val nSlaves: Int, addrMap: AddrMap) (implicit p: Parameters) extends NastiInterconnect { - val temp = Module(new NastiRecursiveInterconnect(nMasters, nSlaves, p(NastiAddrMap))) + val temp = Module(new NastiRecursiveInterconnect(nMasters, nSlaves, addrMap)) temp.io.masters.zip(io.masters).foreach { case (t, i) => t.ar <> i.ar