Vec(Reg) -> Reg(Vec)

uncore/src/main/scala/broadcast.scala

@@ -40,7 +40,7 @@ class L2BroadcastHub extends ManagerCoherenceAgent
   trackerList.map(_.io.incoherent := io.incoherent.toBits)
 
   // Queue to store impending Put data
-  val sdq = Vec.fill(sdqDepth){ Reg(io.iacq().data) }
+  val sdq = Reg(Vec.fill(sdqDepth){io.iacq().data})
   val sdq_val = Reg(init=Bits(0, sdqDepth))
   val sdq_alloc_id = PriorityEncoder(~sdq_val)
   val sdq_rdy = !sdq_val.andR
@@ -69,7 +69,7 @@ class L2BroadcastHub extends ManagerCoherenceAgent
   val voluntary = io.irel().isVoluntary()
   val vwbdq_enq = io.inner.release.fire() && voluntary && io.irel().hasData()
   val (rel_data_cnt, rel_data_done) = Counter(vwbdq_enq, innerDataBeats) //TODO Zero width
-  val vwbdq = Vec.fill(innerDataBeats){ Reg(io.irel().data) } //TODO Assumes nReleaseTransactors == 1 
+  val vwbdq = Reg(Vec.fill(innerDataBeats){io.irel().data}) //TODO Assumes nReleaseTransactors == 1
   when(vwbdq_enq) { vwbdq(rel_data_cnt) := io.irel().data }
 
   // Handle releases, which might be voluntary and might have data
@@ -131,7 +131,7 @@ class BroadcastVoluntaryReleaseTracker(trackerId: Int) extends BroadcastXactTrac
   val state = Reg(init=s_idle)
 
   val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 }))
-  val data_buffer = Vec.fill(innerDataBeats){ Reg(io.irel().data.clone) }
+  val data_buffer = Reg(Vec.fill(innerDataBeats){io.irel().data})
   val coh = ManagerMetadata.onReset
 
   val collect_irel_data = Reg(init=Bool(false))
@@ -210,7 +210,7 @@ class BroadcastAcquireTracker(trackerId: Int) extends BroadcastXactTracker {
   val state = Reg(init=s_idle)
 
   val xact = Reg(Bundle(new AcquireFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 }))
-  val data_buffer = Vec.fill(innerDataBeats){ Reg(io.iacq().data.clone) }
+  val data_buffer = Reg(Vec.fill(innerDataBeats){io.iacq().data})
   val coh = ManagerMetadata.onReset
 
   assert(!(state != s_idle && xact.isBuiltInType() && 

uncore/src/main/scala/cache.scala

@@ -491,7 +491,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int) extends L2XactTracker {
   val state = Reg(init=s_idle)
 
   val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 }))
-  val data_buffer = Vec.fill(innerDataBeats){ Reg(init=UInt(0, width = innerDataBits)) }
+  val data_buffer = Reg(init=Vec.fill(innerDataBeats){UInt(0, width = innerDataBits)})
   val xact_way_en = Reg{ Bits(width = nWays) }
   val xact_old_meta = Reg{ new L2Metadata }
   val coh = xact_old_meta.coh
@@ -586,8 +586,8 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
 
   // State holding transaction metadata
   val xact = Reg(Bundle(new AcquireFromSrc, { case TLId => params(InnerTLId) }))
-  val data_buffer = Vec.fill(innerDataBeats){ Reg(init=UInt(0, width = innerDataBits)) }
+  val data_buffer = Reg(init=Vec.fill(innerDataBeats){UInt(0, width = innerDataBits)})
-  val wmask_buffer = Vec.fill(innerDataBeats){ Reg(init=UInt(0,width = innerDataBits/8)) }
+  val wmask_buffer = Reg(init=Vec.fill(innerDataBeats){UInt(0, width = innerDataBits/8)})
   val xact_tag_match = Reg{ Bool() }
   val xact_way_en = Reg{ Bits(width = nWays) }
   val xact_old_meta = Reg{ new L2Metadata }
@@ -979,7 +979,7 @@ class L2WritebackUnit(trackerId: Int) extends L2XactTracker {
   val state = Reg(init=s_idle)
 
   val xact = Reg(new L2WritebackReq)
-  val data_buffer = Vec.fill(innerDataBeats){ Reg(init=UInt(0, width = innerDataBits)) }
+  val data_buffer = Reg(init=Vec.fill(innerDataBeats){UInt(0, width = innerDataBits)})
   val xact_addr_block = Cat(xact.tag, xact.idx)
 
   val pending_irels =

uncore/src/main/scala/memserdes.scala

@@ -264,7 +264,7 @@ class MemIOTileLinkIOConverter(qDepth: Int) extends TLModule with MIFParameters
     mem_data_q.io.enq.valid := Bool(false)
     val (mif_cnt_out, mif_wrap_out) = Counter(mem_data_q.io.enq.fire(), mifDataBeats)
     val mif_done_out = Reg(init=Bool(false))
-    val tl_buf_out = Vec.fill(tlDataBeats){ Reg(io.tl.acquire.bits.data.clone) }
+    val tl_buf_out = Reg(Vec(io.tl.acquire.bits.data, tlDataBeats))
     val mif_buf_out = Vec.fill(mifDataBeats){ new MemData }
     mif_buf_out := mif_buf_out.fromBits(tl_buf_out.toBits)
     val mif_prog_out = (mif_cnt_out+UInt(1, width = log2Up(mifDataBeats+1)))*UInt(mifDataBits)
@@ -414,7 +414,7 @@ class MemIOTileLinkIOConverter(qDepth: Int) extends TLModule with MIFParameters
   if(tlDataBits != mifDataBits || tlDataBeats != mifDataBeats) {
     val (mif_cnt_in, mif_wrap_in) = Counter(io.mem.resp.fire(), mifDataBeats) // TODO: Assumes all resps have data
     val mif_done_in = Reg(init=Bool(false))
-    val mif_buf_in = Vec.fill(mifDataBeats){ Reg(new MemData) }
+    val mif_buf_in = Reg(Vec(new MemData, mifDataBeats))
     val tl_buf_in = Vec.fill(tlDataBeats){ io.tl.acquire.bits.data.clone }
     tl_buf_in := tl_buf_in.fromBits(mif_buf_in.toBits)
     val tl_prog_in = (tl_cnt_in+UInt(1, width = log2Up(tlDataBeats+1)))*UInt(tlDataBits)