riscv/rocket-chip
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rocketchip: re-add AXI4 interface

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This commit is contained in:
Wesley W. Terpstra
2016-11-22 16:58:24 -08:00
parent c230580157
commit 13190a5de0
7 changed files with 82 additions and 11 deletions
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25
src/main/scala/rocketchip/Periphery.scala
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@ -140,7 +140,7 @@ trait PeripheryMasterAXI4MMIOBundle {
this: TopNetworkBundle {
val outer: PeripheryMasterAXI4MMIO
} =>
val mmio_axi = outer.mmio_axi4.bundleOut
val mmio_axi4 = outer.mmio_axi4.bundleOut
}
trait PeripheryMasterAXI4MMIOModule {
@ -153,6 +153,29 @@ trait PeripheryMasterAXI4MMIOModule {
/////
// PeripherySlaveAXI4 is an example, make your own cake pattern like this one.
trait PeripherySlaveAXI4 extends L2Crossbar {
private val idBits = 8
val l2_axi4 = AXI4BlindInputNode(AXI4MasterPortParameters(
masters = Seq(AXI4MasterParameters(
id = IdRange(0, 1 << idBits)))))
l2.node := AXI4ToTL()(AXI4Fragmenter()(l2_axi4))
}
trait PeripherySlaveAXI4Bundle extends L2CrossbarBundle {
val outer: PeripherySlaveAXI4
val l2_axi4 = outer.l2_axi4.bundleIn
}
trait PeripherySlaveAXI4Module extends L2CrossbarModule {
val outer: PeripherySlaveAXI4
val io: PeripherySlaveAXI4Bundle
// nothing to do
}
/////
trait PeripheryBootROM {
this: TopNetwork =>
val coreplex: CoreplexRISCVPlatform