From 13190a5de0a48739291a265e8f2b15dbaf94151f Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 22 Nov 2016 16:58:24 -0800 Subject: [PATCH] rocketchip: re-add AXI4 interface --- src/main/scala/coreplex/Coreplex.scala | 27 +++++++++++++++++++ src/main/scala/groundtest/TestHarness.scala | 4 +-- src/main/scala/rocketchip/BaseTop.scala | 10 +++++++ src/main/scala/rocketchip/ExampleTop.scala | 5 +++- src/main/scala/rocketchip/Periphery.scala | 25 ++++++++++++++++- .../scala/rocketchip/RocketPlexMaster.scala | 7 ++--- src/main/scala/rocketchip/TestHarness.scala | 15 ++++++++--- 7 files changed, 82 insertions(+), 11 deletions(-) diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala index f577338a..ec2e4673 100644 --- a/src/main/scala/coreplex/Coreplex.scala +++ b/src/main/scala/coreplex/Coreplex.scala @@ -12,32 +12,59 @@ import rocket._ ///// +trait L2MasterPort extends CoreplexNetwork +{ + val module: L2MasterPortModule + val l2in = TLInputNode() + l1tol2.node := l2in +} + +trait L2MasterPortBundle extends CoreplexNetworkBundle +{ + val outer: L2MasterPort + val l2in = outer.l2in.bundleIn +} + +trait L2MasterPortModule extends CoreplexNetworkModule +{ + val outer: L2MasterPort + val io: L2MasterPortBundle +} + +///// + class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex with CoreplexRISCVPlatform + with L2MasterPort with RocketTiles { override lazy val module = new DefaultCoreplexModule(this, () => new DefaultCoreplexBundle(this)) } class DefaultCoreplexBundle[+L <: DefaultCoreplex](_outer: L) extends BaseCoreplexBundle(_outer) with CoreplexRISCVPlatformBundle + with L2MasterPortBundle with RocketTilesBundle class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io) with CoreplexRISCVPlatformModule + with L2MasterPortModule with RocketTilesModule ///// class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex with CoreplexRISCVPlatform + with L2MasterPort with AsyncRocketTiles { override lazy val module = new MultiClockCoreplexModule(this, () => new MultiClockCoreplexBundle(this)) } class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](_outer: L) extends BaseCoreplexBundle(_outer) with CoreplexRISCVPlatformBundle + with L2MasterPortBundle with AsyncRocketTilesBundle class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io) with CoreplexRISCVPlatformModule + with L2MasterPortModule with AsyncRocketTilesModule diff --git a/src/main/scala/groundtest/TestHarness.scala b/src/main/scala/groundtest/TestHarness.scala index 97bc39b6..6cf8cb22 100644 --- a/src/main/scala/groundtest/TestHarness.scala +++ b/src/main/scala/groundtest/TestHarness.scala @@ -18,8 +18,8 @@ class TestHarness(q: Parameters) extends Module { if (dut.io.mem_axi4.nonEmpty) { val memSize = p(ExtMem).size require(memSize % dut.io.mem_axi4.size == 0) - for (axi <- dut.io.mem_axi4) { - Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi <> axi + for (axi4 <- dut.io.mem_axi4) { + Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi4 <> axi4 } } } diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala index 5f2810c7..5879d58e 100644 --- a/src/main/scala/rocketchip/BaseTop.scala +++ b/src/main/scala/rocketchip/BaseTop.scala @@ -67,3 +67,13 @@ class BaseTopBundle[+L <: BaseTop](_outer: L) extends BareTopBundle(_outer) class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io) with TopNetworkModule + +trait L2Crossbar extends TopNetwork { + val l2 = LazyModule(new TLXbar) +} + +trait L2CrossbarBundle extends TopNetworkBundle { +} + +trait L2CrossbarModule extends TopNetworkModule { +} diff --git a/src/main/scala/rocketchip/ExampleTop.scala b/src/main/scala/rocketchip/ExampleTop.scala index c0ec3d3c..6a064104 100644 --- a/src/main/scala/rocketchip/ExampleTop.scala +++ b/src/main/scala/rocketchip/ExampleTop.scala @@ -11,7 +11,8 @@ import rocketchip._ abstract class ExampleTop(implicit p: Parameters) extends BaseTop with PeripheryExtInterrupts with PeripheryMasterAXI4Mem - with PeripheryMasterAXI4MMIO { + with PeripheryMasterAXI4MMIO + with PeripherySlaveAXI4 { override lazy val module = new ExampleTopModule(this, () => new ExampleTopBundle(this)) } @@ -19,11 +20,13 @@ class ExampleTopBundle[+L <: ExampleTop](_outer: L) extends BaseTopBundle(_outer with PeripheryExtInterruptsBundle with PeripheryMasterAXI4MemBundle with PeripheryMasterAXI4MMIOBundle + with PeripherySlaveAXI4Bundle class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io) with PeripheryExtInterruptsModule with PeripheryMasterAXI4MemModule with PeripheryMasterAXI4MMIOModule + with PeripherySlaveAXI4Module class ExampleRocketTop(implicit p: Parameters) extends ExampleTop with PeripheryBootROM diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala index 40b202cc..9458e328 100644 --- a/src/main/scala/rocketchip/Periphery.scala +++ b/src/main/scala/rocketchip/Periphery.scala @@ -140,7 +140,7 @@ trait PeripheryMasterAXI4MMIOBundle { this: TopNetworkBundle { val outer: PeripheryMasterAXI4MMIO } => - val mmio_axi = outer.mmio_axi4.bundleOut + val mmio_axi4 = outer.mmio_axi4.bundleOut } trait PeripheryMasterAXI4MMIOModule { @@ -153,6 +153,29 @@ trait PeripheryMasterAXI4MMIOModule { ///// +// PeripherySlaveAXI4 is an example, make your own cake pattern like this one. +trait PeripherySlaveAXI4 extends L2Crossbar { + private val idBits = 8 + val l2_axi4 = AXI4BlindInputNode(AXI4MasterPortParameters( + masters = Seq(AXI4MasterParameters( + id = IdRange(0, 1 << idBits))))) + + l2.node := AXI4ToTL()(AXI4Fragmenter()(l2_axi4)) +} + +trait PeripherySlaveAXI4Bundle extends L2CrossbarBundle { + val outer: PeripherySlaveAXI4 + val l2_axi4 = outer.l2_axi4.bundleIn +} + +trait PeripherySlaveAXI4Module extends L2CrossbarModule { + val outer: PeripherySlaveAXI4 + val io: PeripherySlaveAXI4Bundle + // nothing to do +} + +///// + trait PeripheryBootROM { this: TopNetwork => val coreplex: CoreplexRISCVPlatform diff --git a/src/main/scala/rocketchip/RocketPlexMaster.scala b/src/main/scala/rocketchip/RocketPlexMaster.scala index 9cbe64ef..a00c39cb 100644 --- a/src/main/scala/rocketchip/RocketPlexMaster.scala +++ b/src/main/scala/rocketchip/RocketPlexMaster.scala @@ -10,22 +10,23 @@ import uncore.devices._ import util._ import coreplex._ -trait RocketPlexMaster extends TopNetwork { +trait RocketPlexMaster extends L2Crossbar { val module: RocketPlexMasterModule val mem: Seq[TLInwardNode] val coreplex = LazyModule(new DefaultCoreplex) + coreplex.l2in := l2.node socBus.node := coreplex.mmio coreplex.mmioInt := intBus.intnode (mem zip coreplex.mem) foreach { case (m, c) => m := c } } -trait RocketPlexMasterBundle extends TopNetworkBundle { +trait RocketPlexMasterBundle extends L2CrossbarBundle { val outer: RocketPlexMaster } -trait RocketPlexMasterModule extends TopNetworkModule { +trait RocketPlexMasterModule extends L2CrossbarModule { val outer: RocketPlexMaster val io: RocketPlexMasterBundle } diff --git a/src/main/scala/rocketchip/TestHarness.scala b/src/main/scala/rocketchip/TestHarness.scala index 465183f9..727315e9 100644 --- a/src/main/scala/rocketchip/TestHarness.scala +++ b/src/main/scala/rocketchip/TestHarness.scala @@ -22,15 +22,22 @@ class TestHarness(q: Parameters) extends Module { if (dut.io.mem_axi4.nonEmpty) { val memSize = p(ExtMem).size require(memSize % dut.io.mem_axi4.size == 0) - for (axi <- dut.io.mem_axi4) { - Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi <> axi + for (axi4 <- dut.io.mem_axi4) { + Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi4 <> axi4 } } val dtm = Module(new SimDTM).connect(clock, reset, dut.io.debug, io.success) val mmio_sim = Module(LazyModule(new SimAXIMem(4096)).module) - mmio_sim.io.axi <> dut.io.mmio_axi + mmio_sim.io.axi4 <> dut.io.mmio_axi4 + + val l2_axi4 = dut.io.l2_axi4(0) + l2_axi4.ar.valid := Bool(false) + l2_axi4.aw.valid := Bool(false) + l2_axi4.w .valid := Bool(false) + l2_axi4.r .ready := Bool(true) + l2_axi4.b .ready := Bool(true) } class SimAXIMem(size: BigInt)(implicit p: Parameters) extends LazyModule { @@ -42,7 +49,7 @@ class SimAXIMem(size: BigInt)(implicit p: Parameters) extends LazyModule { lazy val module = new LazyModuleImp(this) { val io = new Bundle { - val axi = node.bundleIn + val axi4 = node.bundleIn } } }