riscv/rocket-chip
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rocketchip: re-add AXI4 interface

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This commit is contained in:
Wesley W. Terpstra
2016-11-22 16:58:24 -08:00
parent c230580157
commit 13190a5de0
7 changed files with 82 additions and 11 deletions
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5
src/main/scala/rocketchip/ExampleTop.scala
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@ -11,7 +11,8 @@ import rocketchip._
abstract class ExampleTop(implicit p: Parameters) extends BaseTop
with PeripheryExtInterrupts
with PeripheryMasterAXI4Mem
with PeripheryMasterAXI4MMIO {
with PeripheryMasterAXI4MMIO
with PeripherySlaveAXI4 {
override lazy val module = new ExampleTopModule(this, () => new ExampleTopBundle(this))
}
@ -19,11 +20,13 @@ class ExampleTopBundle[+L <: ExampleTop](_outer: L) extends BaseTopBundle(_outer
with PeripheryExtInterruptsBundle
with PeripheryMasterAXI4MemBundle
with PeripheryMasterAXI4MMIOBundle
with PeripherySlaveAXI4Bundle
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
with PeripheryExtInterruptsModule
with PeripheryMasterAXI4MemModule
with PeripheryMasterAXI4MMIOModule
with PeripherySlaveAXI4Module
class ExampleRocketTop(implicit p: Parameters) extends ExampleTop
with PeripheryBootROM