rocketchip: re-add AXI4 interface
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@ -18,8 +18,8 @@ class TestHarness(q: Parameters) extends Module {
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if (dut.io.mem_axi4.nonEmpty) {
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val memSize = p(ExtMem).size
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require(memSize % dut.io.mem_axi4.size == 0)
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for (axi <- dut.io.mem_axi4) {
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Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi <> axi
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for (axi4 <- dut.io.mem_axi4) {
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Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi4 <> axi4
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}
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}
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}
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