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rocketchip: re-add AXI4 interface

This commit is contained in:
Wesley W. Terpstra
2016-11-22 16:58:24 -08:00
parent c230580157
commit 13190a5de0
7 changed files with 82 additions and 11 deletions

View File

@ -18,8 +18,8 @@ class TestHarness(q: Parameters) extends Module {
if (dut.io.mem_axi4.nonEmpty) {
val memSize = p(ExtMem).size
require(memSize % dut.io.mem_axi4.size == 0)
for (axi <- dut.io.mem_axi4) {
Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi <> axi
for (axi4 <- dut.io.mem_axi4) {
Module(LazyModule(new SimAXIMem(memSize / dut.io.mem_axi4.size)).module).io.axi4 <> axi4
}
}
}