From a42832fc708e6573fec89eba5124be897cc1f016 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Thu, 25 Jun 2015 10:40:59 -0700 Subject: [PATCH 1/2] Fix fpga_mem_gen for Python 2 and 3 Environments Two quick fixes that enable fpga_mem_gen to work with either Python 2 or Python 3: * Change an `xrange` instance to `range` * Wrap the arguments of a bare `print` in parentheses --- fsim/fpga_mem_gen | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fsim/fpga_mem_gen b/fsim/fpga_mem_gen index dafb7a92..2c9e2490 100755 --- a/fsim/fpga_mem_gen +++ b/fsim/fpga_mem_gen @@ -53,7 +53,7 @@ def parse_line(line): mask_gran = 1 tokens = line.split() i = 0 - for i in xrange(0,len(tokens),2): + for i in range(0,len(tokens),2): s = tokens[i] if s == 'name': name = tokens[i+1] @@ -188,7 +188,7 @@ def main(): if len(sys.argv) < 2: sys.exit('Please give a .conf file as input') for line in open(sys.argv[1]): - print gen_mem(*parse_line(line)) + print(gen_mem(*parse_line(line))) if __name__ == '__main__': From b4cd8c5981337be4086680c687dc219c7013fc22 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Thu, 25 Jun 2015 12:48:31 -0700 Subject: [PATCH 2/2] Fix vlsi_mem_gen for Python 2 or 3 --- vsim/vlsi_mem_gen | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vsim/vlsi_mem_gen b/vsim/vlsi_mem_gen index e15415e8..09b7d077 100755 --- a/vsim/vlsi_mem_gen +++ b/vsim/vlsi_mem_gen @@ -15,7 +15,7 @@ def parse_line(line): mask_gran = 1 tokens = line.split() i = 0 - for i in xrange(0,len(tokens),2): + for i in range(0,len(tokens),2): s = tokens[i] if s == 'name': name = tokens[i+1] @@ -130,7 +130,7 @@ def gen_mem(name, width, depth, ports): %s\n\ end\n\ %s\n" % ('\n '.join(decl), '\n '.join(sequential), '\n '.join(combinational)) - + s = "module %s(\n\ %s\n\ );\n\ @@ -144,7 +144,7 @@ def main(): if len(sys.argv) < 2: sys.exit('Please give a .conf file as input') for line in open(sys.argv[1]): - print gen_mem(*parse_line(line)) + print(gen_mem(*parse_line(line))) if __name__ == '__main__': main()