riscv/rocket-chip
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clock gate s2 registers in the frontend

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This commit is contained in:
Yunsup Lee 2013-05-21 18:59:21 -07:00
parent c837c1d800
commit 11133d6d4c
1 changed files with 5 additions and 3 deletions
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2
rocket/src/main/scala/icache.scala
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@ -81,10 +81,12 @@ class Frontend(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) ex
s1_same_block := s0_same_block && !tlb.io.resp.miss s1_same_block := s0_same_block && !tlb.io.resp.miss
s1_pc := npc s1_pc := npc
s2_valid := !icmiss s2_valid := !icmiss
when (!icmiss) {
s2_pc := s1_pc s2_pc := s1_pc
s2_btb_hit := btb.io.hit s2_btb_hit := btb.io.hit
s2_xcpt_if := tlb.io.resp.xcpt_if s2_xcpt_if := tlb.io.resp.xcpt_if
} }
}
when (io.cpu.req.valid) { when (io.cpu.req.valid) {
s1_same_block := Bool(false) s1_same_block := Bool(false)
s1_pc := io.cpu.req.bits.pc s1_pc := io.cpu.req.bits.pc