From 11133d6d4c926f8aa2fcb555e812f18375ec829b Mon Sep 17 00:00:00 2001
From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Tue, 21 May 2013 18:59:21 -0700
Subject: [PATCH] clock gate s2 registers in the frontend

---
 rocket/src/main/scala/icache.scala | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index f4febe9d..374bae6b 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -81,9 +81,11 @@ class Frontend(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) ex
     s1_same_block := s0_same_block && !tlb.io.resp.miss
     s1_pc := npc
     s2_valid := !icmiss
-    s2_pc := s1_pc
-    s2_btb_hit := btb.io.hit
-    s2_xcpt_if := tlb.io.resp.xcpt_if
+    when (!icmiss) {
+      s2_pc := s1_pc
+      s2_btb_hit := btb.io.hit
+      s2_xcpt_if := tlb.io.resp.xcpt_if
+    }
   }
   when (io.cpu.req.valid) {
     s1_same_block := Bool(false)