riscv/rocket-chip
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Revert "Add early out to multiplier"

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This broke recently and I don't have time to figure out why.
This commit is contained in:
Andrew Waterman 2013-09-15 04:15:32 -07:00
parent 88d1c47665
commit 110e53cb48
1 changed files with 2 additions and 5 deletions
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7
rocket/src/main/scala/divider.scala
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@ -54,14 +54,11 @@ class MulDiv(mulUnroll: Int = 1, earlyOut: Boolean = false)(implicit conf: Rocke
val accum = mulReg(2*mulw,mulw).toSInt val accum = mulReg(2*mulw,mulw).toSInt
val mpcand = divisor.toSInt val mpcand = divisor.toSInt
val prod = mplier(mulUnroll-1,0) * mpcand + accum val prod = mplier(mulUnroll-1,0) * mpcand + accum
val eOut = Bool(earlyOut) && count > 0 && val nextMulReg = Cat(prod, mplier(mulw-1,mulUnroll)).toUInt
(0 until mulw/mulUnroll).map(i => i > mulw/mulUnroll-1-count || mplier((i+1)*mulUnroll-1,i*mulUnroll) === 0).reduce(_&&_)
val eOutValue = mulReg >> (mulw/mulUnroll-count)(log2Up(mulw/mulUnroll)-1,0)*mulUnroll
val nextMulReg = Mux(eOut, eOutValue, Cat(prod, mplier(mulw-1,mulUnroll)))
remainder := Cat(nextMulReg >> w, Bool(false), nextMulReg(w-1,0)).toSInt remainder := Cat(nextMulReg >> w, Bool(false), nextMulReg(w-1,0)).toSInt
count := count + 1 count := count + 1
when (count === mulw/mulUnroll-1 || eOut) { when (count === mulw/mulUnroll-1) {
state := s_done state := s_done
when (AVec(FN_MULH, FN_MULHU, FN_MULHSU) contains req.fn) { when (AVec(FN_MULH, FN_MULHU, FN_MULHSU) contains req.fn) {
state := s_move_rem state := s_move_rem