From 110e53cb48f6fbb3b77736e05e07e67c693f6db2 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 15 Sep 2013 04:15:32 -0700 Subject: [PATCH] Revert "Add early out to multiplier" This broke recently and I don't have time to figure out why. --- rocket/src/main/scala/divider.scala | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/rocket/src/main/scala/divider.scala b/rocket/src/main/scala/divider.scala index c18e47d6..1ea4dd29 100644 --- a/rocket/src/main/scala/divider.scala +++ b/rocket/src/main/scala/divider.scala @@ -54,14 +54,11 @@ class MulDiv(mulUnroll: Int = 1, earlyOut: Boolean = false)(implicit conf: Rocke val accum = mulReg(2*mulw,mulw).toSInt val mpcand = divisor.toSInt val prod = mplier(mulUnroll-1,0) * mpcand + accum - val eOut = Bool(earlyOut) && count > 0 && - (0 until mulw/mulUnroll).map(i => i > mulw/mulUnroll-1-count || mplier((i+1)*mulUnroll-1,i*mulUnroll) === 0).reduce(_&&_) - val eOutValue = mulReg >> (mulw/mulUnroll-count)(log2Up(mulw/mulUnroll)-1,0)*mulUnroll - val nextMulReg = Mux(eOut, eOutValue, Cat(prod, mplier(mulw-1,mulUnroll))) + val nextMulReg = Cat(prod, mplier(mulw-1,mulUnroll)).toUInt remainder := Cat(nextMulReg >> w, Bool(false), nextMulReg(w-1,0)).toSInt count := count + 1 - when (count === mulw/mulUnroll-1 || eOut) { + when (count === mulw/mulUnroll-1) { state := s_done when (AVec(FN_MULH, FN_MULHU, FN_MULHSU) contains req.fn) { state := s_move_rem