riscv/rocket-chip
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allow coreplex to take in more than 1 bus port

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This commit is contained in:
Howard Mao
2016-08-18 10:34:01 -07:00
parent de316643d1
commit 10190197c3
7 changed files with 19 additions and 18 deletions
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2
src/main/scala/Configs.scala
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@ -132,7 +132,7 @@ class BasePlatformConfig extends Config (
case ExportMMIOPort => (site(ExtraDevices).size + site(ExtMMIOPorts).size) > 0
case AsyncBusChannels => false
case NExtBusAXIChannels => 0
case ExportBusPort => site(NExtBusAXIChannels) > 0
case NBusPorts => if (site(NExtBusAXIChannels) > 1) 1 else 0
case ConnectExtraPorts =>
(out: Bundle, in: Bundle, p: Parameters) => out <> in

11
src/main/scala/RocketChip.scala
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@ -57,7 +57,6 @@ trait HasTopLevelParameters {
lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
lazy val exportBus = p(ExportBusPort)
lazy val exportMMIO = p(ExportMMIOPort)
}
@ -135,7 +134,7 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
if (exportMMIO) { periphery.io.mmio_in.get <> coreplex.io.mmio.get }
periphery.io.mem_in <> coreplex.io.mem
if (exportBus) { coreplex.io.bus.get <> periphery.io.bus_out.get }
coreplex.io.bus <> periphery.io.bus_out
coreplex.io.debug <>
(if (p(AsyncDebugBus))
@ -179,7 +178,7 @@ class Periphery(implicit val p: Parameters) extends Module
with HasTopLevelParameters {
val io = new Bundle {
val mem_in = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams)).flip
val bus_out = if (exportBus) Some(new ClientUncachedTileLinkIO()(innerParams)) else None
val bus_out = Vec(p(NBusPorts), new ClientUncachedTileLinkIO()(innerParams))
val mmio_in = if (exportMMIO) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams).flip) else None
val mem_axi = Vec(nMemAXIChannels, new NastiIO)
val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO)
@ -191,12 +190,14 @@ class Periphery(implicit val p: Parameters) extends Module
val extra = p(ExtraTopPorts)(p)
}
io.bus_out.map { tl_out =>
require(io.bus_out.size <= 1)
if (io.bus_out.size > 0) {
val conv = Module(new TileLinkIONastiIOConverter)
val arb = Module(new NastiArbiter(p(NExtBusAXIChannels)))
arb.io.master <> io.bus_axi
conv.io.nasti <> conv.io.tl
tl_out <> conv.io.tl
io.bus_out.head <> conv.io.tl
}
def connectExternalMMIO(ports: Seq[ClientUncachedTileLinkIO])(implicit p: Parameters) {