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allow coreplex to take in more than 1 bus port

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This commit is contained in:
Howard Mao
2016-08-18 10:34:01 -07:00
parent de316643d1
commit 10190197c3
7 changed files with 19 additions and 18 deletions
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coreplex/src/main/scala/Configs.scala
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@ -160,7 +160,7 @@ class BaseCoreplexConfig extends Config (
else new MESICoherence(site(L2DirectoryRepresentation))),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
nCachingClients = site(NCachedTileLinkPorts),
nCachelessClients = (if (site(ExportBusPort)) 1 else 0) + site(NUncachedTileLinkPorts),
nCachelessClients = site(NBusPorts) + site(NUncachedTileLinkPorts),
maxClientXacts = max_int(
// L1 cache
site(NMSHRs) + 1 /* IOMSHR */,