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Chisel3 compatibility fixes

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This commit is contained in:
Andrew Waterman 2015-09-30 14:36:49 -07:00
parent 1e7f656527
commit 0fe16ac1c0
1 changed files with 1 additions and 1 deletions
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uncore/src/main/scala/htif.scala
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@ -86,7 +86,7 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
val rx_word_count = (rx_count >> log2Up(short_request_bits/w)) val rx_word_count = (rx_count >> log2Up(short_request_bits/w))
val rx_word_done = io.host.in.valid && rx_count(log2Up(short_request_bits/w)-1,0).andR val rx_word_done = io.host.in.valid && rx_count(log2Up(short_request_bits/w)-1,0).andR
val packet_ram_depth = long_request_bits/short_request_bits-1 val packet_ram_depth = long_request_bits/short_request_bits-1
val packet_ram = Mem(Bits(width = short_request_bits), packet_ram_depth) val packet_ram = Mem(packet_ram_depth, Bits(width = short_request_bits))
when (rx_word_done && io.host.in.ready) { when (rx_word_done && io.host.in.ready) {
packet_ram(rx_word_count(log2Up(packet_ram_depth)-1,0) - UInt(1)) := rx_shifter_in packet_ram(rx_word_count(log2Up(packet_ram_depth)-1,0) - UInt(1)) := rx_shifter_in
} }