From 0fe16ac1c01f7499fd7cf67bb236394df76bbab8 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 30 Sep 2015 14:36:49 -0700 Subject: [PATCH] Chisel3 compatibility fixes --- uncore/src/main/scala/htif.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/uncore/src/main/scala/htif.scala b/uncore/src/main/scala/htif.scala index 20bd317f..de6e0c33 100644 --- a/uncore/src/main/scala/htif.scala +++ b/uncore/src/main/scala/htif.scala @@ -86,7 +86,7 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters { val rx_word_count = (rx_count >> log2Up(short_request_bits/w)) val rx_word_done = io.host.in.valid && rx_count(log2Up(short_request_bits/w)-1,0).andR val packet_ram_depth = long_request_bits/short_request_bits-1 - val packet_ram = Mem(Bits(width = short_request_bits), packet_ram_depth) + val packet_ram = Mem(packet_ram_depth, Bits(width = short_request_bits)) when (rx_word_done && io.host.in.ready) { packet_ram(rx_word_count(log2Up(packet_ram_depth)-1,0) - UInt(1)) := rx_shifter_in }