riscv/rocket-chip
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Remove IPI network

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This is now provided via MMIO.
This commit is contained in:
Andrew Waterman
2015-11-16 21:51:43 -08:00
parent 213c1a4c81
commit 0f092b9b59
2 changed files with 10 additions and 9 deletions
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13
rocket/src/main/scala/csr.scala
View File

@@ -203,6 +203,8 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
CSRs.mtdeleg -> UInt(0), CSRs.mtdeleg -> UInt(0),
CSRs.mreset -> UInt(0), CSRs.mreset -> UInt(0),
CSRs.mtvec -> UInt(MTVEC), CSRs.mtvec -> UInt(MTVEC),
CSRs.miobase -> UInt(p(junctions.MMIOBase)),
CSRs.mipi -> UInt(0),
CSRs.mip -> reg_mip.toBits, CSRs.mip -> reg_mip.toBits,
CSRs.mie -> reg_mie.toBits, CSRs.mie -> reg_mie.toBits,
CSRs.mscratch -> reg_mscratch, CSRs.mscratch -> reg_mscratch,
@@ -211,7 +213,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
CSRs.mcause -> reg_mcause, CSRs.mcause -> reg_mcause,
CSRs.mtimecmp -> reg_mtimecmp, CSRs.mtimecmp -> reg_mtimecmp,
CSRs.mhartid -> io.host.id, CSRs.mhartid -> io.host.id,
CSRs.send_ipi -> io.host.id, /* don't care */
CSRs.stats -> reg_stats, CSRs.stats -> reg_stats,
CSRs.mtohost -> reg_tohost, CSRs.mtohost -> reg_tohost,
CSRs.mfromhost -> reg_fromhost) CSRs.mfromhost -> reg_fromhost)
@@ -353,9 +354,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
} }
io.time := reg_cycle io.time := reg_cycle
io.host.ipi_req.valid := cpu_wen && decoded_addr(CSRs.send_ipi) io.csr_replay := false
io.host.ipi_req.bits := io.rw.wdata
io.csr_replay := io.host.ipi_req.valid && !io.host.ipi_req.ready
io.csr_stall := reg_wfi io.csr_stall := reg_wfi
when (host_csr_req_fire && !host_csr_bits.rw && decoded_addr(CSRs.mtohost)) { reg_tohost := UInt(0) } when (host_csr_req_fire && !host_csr_bits.rw && decoded_addr(CSRs.mtohost)) { reg_tohost := UInt(0) }
@@ -400,6 +399,9 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
} }
reg_mip.msip := new_mip.msip reg_mip.msip := new_mip.msip
} }
when (decoded_addr(CSRs.mipi)) {
reg_mip.msip := true
}
when (decoded_addr(CSRs.mie)) { when (decoded_addr(CSRs.mie)) {
val new_mie = new MIP().fromBits(wdata) val new_mie = new MIP().fromBits(wdata)
if (usingVM) { if (usingVM) {
@@ -449,9 +451,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
} }
} }
io.host.ipi_rep.ready := true
when (io.host.ipi_rep.valid) { reg_mip.msip := true }
when(this.reset) { when(this.reset) {
reg_mstatus.zero1 := 0 reg_mstatus.zero1 := 0
reg_mstatus.zero2 := 0 reg_mstatus.zero2 := 0

6
rocket/src/main/scala/instructions.scala
View File

@@ -299,7 +299,8 @@ object CSRs {
val mtohost = 0x780 val mtohost = 0x780
val mfromhost = 0x781 val mfromhost = 0x781
val mreset = 0x782 val mreset = 0x782
val send_ipi = 0x783 val mipi = 0x783
val miobase = 0x784
val cycleh = 0xc80 val cycleh = 0xc80
val timeh = 0xc81 val timeh = 0xc81
val instreth = 0xc82 val instreth = 0xc82
@@ -367,7 +368,8 @@ object CSRs {
res += mtohost res += mtohost
res += mfromhost res += mfromhost
res += mreset res += mreset
res += send_ipi res += mipi
res += miobase
res.toArray res.toArray
} }
val all32 = { val all32 = {