diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index 627831a3..efaf25b8 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -203,6 +203,8 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
     CSRs.mtdeleg -> UInt(0),
     CSRs.mreset -> UInt(0),
     CSRs.mtvec -> UInt(MTVEC),
+    CSRs.miobase -> UInt(p(junctions.MMIOBase)),
+    CSRs.mipi -> UInt(0),
     CSRs.mip -> reg_mip.toBits,
     CSRs.mie -> reg_mie.toBits,
     CSRs.mscratch -> reg_mscratch,
@@ -211,7 +213,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
     CSRs.mcause -> reg_mcause,
     CSRs.mtimecmp -> reg_mtimecmp,
     CSRs.mhartid -> io.host.id,
-    CSRs.send_ipi -> io.host.id, /* don't care */
     CSRs.stats -> reg_stats,
     CSRs.mtohost -> reg_tohost,
     CSRs.mfromhost -> reg_fromhost)
@@ -353,9 +354,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
   }
 
   io.time := reg_cycle
-  io.host.ipi_req.valid := cpu_wen && decoded_addr(CSRs.send_ipi)
-  io.host.ipi_req.bits := io.rw.wdata
-  io.csr_replay := io.host.ipi_req.valid && !io.host.ipi_req.ready
+  io.csr_replay := false
   io.csr_stall := reg_wfi
 
   when (host_csr_req_fire && !host_csr_bits.rw && decoded_addr(CSRs.mtohost)) { reg_tohost := UInt(0) }
@@ -400,6 +399,9 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
       }
       reg_mip.msip := new_mip.msip
     }
+    when (decoded_addr(CSRs.mipi)) {
+      reg_mip.msip := true
+    }
     when (decoded_addr(CSRs.mie)) {
       val new_mie = new MIP().fromBits(wdata)
       if (usingVM) {
@@ -449,9 +451,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
     }
   }
 
-  io.host.ipi_rep.ready := true
-  when (io.host.ipi_rep.valid) { reg_mip.msip := true }
-
   when(this.reset) {
     reg_mstatus.zero1 := 0
     reg_mstatus.zero2 := 0
diff --git a/rocket/src/main/scala/instructions.scala b/rocket/src/main/scala/instructions.scala
index b5ab974f..b383e385 100644
--- a/rocket/src/main/scala/instructions.scala
+++ b/rocket/src/main/scala/instructions.scala
@@ -299,7 +299,8 @@ object CSRs {
   val mtohost = 0x780
   val mfromhost = 0x781
   val mreset = 0x782
-  val send_ipi = 0x783
+  val mipi = 0x783
+  val miobase = 0x784
   val cycleh = 0xc80
   val timeh = 0xc81
   val instreth = 0xc82
@@ -367,7 +368,8 @@ object CSRs {
     res += mtohost
     res += mfromhost
     res += mreset
-    res += send_ipi
+    res += mipi
+    res += miobase
     res.toArray
   }
   val all32 = {