riscv/rocket-chip
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Bump hardfloat, giving us the 5th rounding mode finally!

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Andrew Waterman 2017-03-26 12:27:43 -07:00 committed by Andrew Waterman
parent e710e32f10
commit 0e2b780089
2 changed files with 2 additions and 2 deletions
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2
hardfloat

@ -1 +1 @@
Subproject commit f38b8beeb3fbce40ee3d9c1e132c8f60ed05f4aa Subproject commit 7f9ab280fee705b3d32c071209fd9022ddfc13d4

2
src/main/scala/tile/FPU.scala
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@ -690,7 +690,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === UInt(x._2)))) io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === UInt(x._2))))
io.sboard_clra := waddr io.sboard_clra := waddr
// we don't currently support round-max-magnitude (rm=4) // we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14) && (io.inst(13,12) < 3 || io.fcsr_rm >= 4) io.illegal_rm := io.inst(14,12).isOneOf(5, 6) || io.inst(14,12) === 7 && io.fcsr_rm >= 5
divSqrt_wdata := 0 divSqrt_wdata := 0
divSqrt_flags := 0 divSqrt_flags := 0