745 lines
27 KiB
Scala
745 lines
27 KiB
Scala
// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package tile
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import Chisel._
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import Chisel.ImplicitConversions._
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import FPConstants._
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import rocket.DecodeLogic
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import rocket.Instructions._
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import uncore.constants.MemoryOpConstants._
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import config._
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import util._
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case class FPUParams(
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divSqrt: Boolean = true,
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sfmaLatency: Int = 3,
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dfmaLatency: Int = 4
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)
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object FPConstants
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{
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def FCMD_ADD = BitPat("b0??00")
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def FCMD_SUB = BitPat("b0??01")
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def FCMD_MUL = BitPat("b0??10")
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def FCMD_MADD = BitPat("b1??00")
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def FCMD_MSUB = BitPat("b1??01")
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def FCMD_NMSUB = BitPat("b1??10")
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def FCMD_NMADD = BitPat("b1??11")
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def FCMD_DIV = BitPat("b?0011")
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def FCMD_SQRT = BitPat("b?1011")
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def FCMD_SGNJ = BitPat("b??1?0")
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def FCMD_MINMAX = BitPat("b?01?1")
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def FCMD_CVT_FF = BitPat("b??0??")
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def FCMD_CVT_IF = BitPat("b?10??")
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def FCMD_CMP = BitPat("b?01??")
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def FCMD_MV_XF = BitPat("b?11??")
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def FCMD_CVT_FI = BitPat("b??0??")
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def FCMD_MV_FX = BitPat("b??1??")
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def FCMD_X = BitPat("b?????")
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val FCMD_WIDTH = 5
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val RM_SZ = 3
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val FLAGS_SZ = 5
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}
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trait HasFPUCtrlSigs {
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val cmd = Bits(width = FCMD_WIDTH)
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val ldst = Bool()
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val wen = Bool()
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val ren1 = Bool()
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val ren2 = Bool()
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val ren3 = Bool()
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val swap12 = Bool()
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val swap23 = Bool()
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val single = Bool()
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val fromint = Bool()
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val toint = Bool()
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val fastpipe = Bool()
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val fma = Bool()
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val div = Bool()
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val sqrt = Bool()
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val wflags = Bool()
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}
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class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
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class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
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val io = new Bundle {
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val inst = Bits(INPUT, 32)
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val sigs = new FPUCtrlSigs().asOutput
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}
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val default = List(FCMD_X, X,X,X,X,X,X,X,X,X,X,X,X,X,X,X)
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val f =
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Array(FLW -> List(FCMD_X, Y,Y,N,N,N,X,X,Y,N,N,N,N,N,N,N),
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FSW -> List(FCMD_MV_XF, Y,N,N,Y,N,Y,X,Y,N,Y,N,N,N,N,N),
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FMV_S_X -> List(FCMD_MV_FX, N,Y,N,N,N,X,X,Y,Y,N,N,N,N,N,N),
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FCVT_S_W -> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,Y,Y,N,N,N,N,N,Y),
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FCVT_S_WU-> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,Y,Y,N,N,N,N,N,Y),
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FCVT_S_L -> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,Y,Y,N,N,N,N,N,Y),
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FCVT_S_LU-> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,Y,Y,N,N,N,N,N,Y),
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FMV_X_S -> List(FCMD_MV_XF, N,N,Y,N,N,N,X,Y,N,Y,N,N,N,N,N),
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FCLASS_S -> List(FCMD_MV_XF, N,N,Y,N,N,N,X,Y,N,Y,N,N,N,N,N),
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FCVT_W_S -> List(FCMD_CVT_IF, N,N,Y,N,N,N,X,Y,N,Y,N,N,N,N,Y),
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FCVT_WU_S-> List(FCMD_CVT_IF, N,N,Y,N,N,N,X,Y,N,Y,N,N,N,N,Y),
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FCVT_L_S -> List(FCMD_CVT_IF, N,N,Y,N,N,N,X,Y,N,Y,N,N,N,N,Y),
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FCVT_LU_S-> List(FCMD_CVT_IF, N,N,Y,N,N,N,X,Y,N,Y,N,N,N,N,Y),
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FEQ_S -> List(FCMD_CMP, N,N,Y,Y,N,N,N,Y,N,Y,N,N,N,N,Y),
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FLT_S -> List(FCMD_CMP, N,N,Y,Y,N,N,N,Y,N,Y,N,N,N,N,Y),
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FLE_S -> List(FCMD_CMP, N,N,Y,Y,N,N,N,Y,N,Y,N,N,N,N,Y),
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FSGNJ_S -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,Y,N,N,Y,N,N,N,N),
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FSGNJN_S -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,Y,N,N,Y,N,N,N,N),
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FSGNJX_S -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,Y,N,N,Y,N,N,N,N),
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FMIN_S -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,N,Y,N,N,Y,N,N,N,Y),
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FMAX_S -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,N,Y,N,N,Y,N,N,N,Y),
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FADD_S -> List(FCMD_ADD, N,Y,Y,Y,N,N,Y,Y,N,N,N,Y,N,N,Y),
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FSUB_S -> List(FCMD_SUB, N,Y,Y,Y,N,N,Y,Y,N,N,N,Y,N,N,Y),
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FMUL_S -> List(FCMD_MUL, N,Y,Y,Y,N,N,N,Y,N,N,N,Y,N,N,Y),
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FMADD_S -> List(FCMD_MADD, N,Y,Y,Y,Y,N,N,Y,N,N,N,Y,N,N,Y),
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FMSUB_S -> List(FCMD_MSUB, N,Y,Y,Y,Y,N,N,Y,N,N,N,Y,N,N,Y),
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FNMADD_S -> List(FCMD_NMADD, N,Y,Y,Y,Y,N,N,Y,N,N,N,Y,N,N,Y),
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FNMSUB_S -> List(FCMD_NMSUB, N,Y,Y,Y,Y,N,N,Y,N,N,N,Y,N,N,Y),
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FDIV_S -> List(FCMD_DIV, N,Y,Y,Y,N,N,N,Y,N,N,N,N,Y,N,Y),
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FSQRT_S -> List(FCMD_SQRT, N,Y,Y,N,N,Y,X,Y,N,N,N,N,N,Y,Y))
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val d =
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Array(FLD -> List(FCMD_X, Y,Y,N,N,N,X,X,N,N,N,N,N,N,N,N),
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FSD -> List(FCMD_MV_XF, Y,N,N,Y,N,Y,X,N,N,Y,N,N,N,N,N),
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FMV_D_X -> List(FCMD_MV_FX, N,Y,N,N,N,X,X,N,Y,N,N,N,N,N,N),
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FCVT_D_W -> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,N,Y,N,N,N,N,N,Y),
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FCVT_D_WU-> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,N,Y,N,N,N,N,N,Y),
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FCVT_D_L -> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,N,Y,N,N,N,N,N,Y),
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FCVT_D_LU-> List(FCMD_CVT_FI, N,Y,N,N,N,X,X,N,Y,N,N,N,N,N,Y),
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FMV_X_D -> List(FCMD_MV_XF, N,N,Y,N,N,N,X,N,N,Y,N,N,N,N,N),
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FCLASS_D -> List(FCMD_MV_XF, N,N,Y,N,N,N,X,N,N,Y,N,N,N,N,N),
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FCVT_W_D -> List(FCMD_CVT_IF, N,N,Y,N,N,N,X,N,N,Y,N,N,N,N,Y),
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FCVT_WU_D-> List(FCMD_CVT_IF, N,N,Y,N,N,N,X,N,N,Y,N,N,N,N,Y),
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FCVT_L_D -> List(FCMD_CVT_IF, N,N,Y,N,N,N,X,N,N,Y,N,N,N,N,Y),
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FCVT_LU_D-> List(FCMD_CVT_IF, N,N,Y,N,N,N,X,N,N,Y,N,N,N,N,Y),
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FCVT_S_D -> List(FCMD_CVT_FF, N,Y,Y,N,N,N,X,Y,N,N,Y,N,N,N,Y),
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FCVT_D_S -> List(FCMD_CVT_FF, N,Y,Y,N,N,N,X,N,N,N,Y,N,N,N,Y),
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FEQ_D -> List(FCMD_CMP, N,N,Y,Y,N,N,N,N,N,Y,N,N,N,N,Y),
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FLT_D -> List(FCMD_CMP, N,N,Y,Y,N,N,N,N,N,Y,N,N,N,N,Y),
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FLE_D -> List(FCMD_CMP, N,N,Y,Y,N,N,N,N,N,Y,N,N,N,N,Y),
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FSGNJ_D -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,N,N,N,Y,N,N,N,N),
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FSGNJN_D -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,N,N,N,Y,N,N,N,N),
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FSGNJX_D -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,N,N,N,Y,N,N,N,N),
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FMIN_D -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,N,N,N,N,Y,N,N,N,Y),
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FMAX_D -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,N,N,N,N,Y,N,N,N,Y),
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FADD_D -> List(FCMD_ADD, N,Y,Y,Y,N,N,Y,N,N,N,N,Y,N,N,Y),
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FSUB_D -> List(FCMD_SUB, N,Y,Y,Y,N,N,Y,N,N,N,N,Y,N,N,Y),
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FMUL_D -> List(FCMD_MUL, N,Y,Y,Y,N,N,N,N,N,N,N,Y,N,N,Y),
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FMADD_D -> List(FCMD_MADD, N,Y,Y,Y,Y,N,N,N,N,N,N,Y,N,N,Y),
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FMSUB_D -> List(FCMD_MSUB, N,Y,Y,Y,Y,N,N,N,N,N,N,Y,N,N,Y),
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FNMADD_D -> List(FCMD_NMADD, N,Y,Y,Y,Y,N,N,N,N,N,N,Y,N,N,Y),
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FNMSUB_D -> List(FCMD_NMSUB, N,Y,Y,Y,Y,N,N,N,N,N,N,Y,N,N,Y),
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FDIV_D -> List(FCMD_DIV, N,Y,Y,Y,N,N,N,N,N,N,N,N,Y,N,Y),
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FSQRT_D -> List(FCMD_SQRT, N,Y,Y,N,N,Y,X,N,N,N,N,N,N,Y,Y))
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val insns = fLen match {
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case 32 => f
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case 64 => f ++ d
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}
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val decoder = DecodeLogic(io.inst, default, insns)
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val s = io.sigs
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val sigs = Seq(s.cmd, s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
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s.swap23, s.single, s.fromint, s.toint, s.fastpipe, s.fma,
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s.div, s.sqrt, s.wflags)
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sigs zip decoder map {case(s,d) => s := d}
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}
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class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
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val inst = Bits(INPUT, 32)
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val fromint_data = Bits(INPUT, xLen)
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val fcsr_rm = Bits(INPUT, FPConstants.RM_SZ)
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val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ))
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val store_data = Bits(OUTPUT, fLen)
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val toint_data = Bits(OUTPUT, xLen)
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val dmem_resp_val = Bool(INPUT)
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val dmem_resp_type = Bits(INPUT, 3)
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val dmem_resp_tag = UInt(INPUT, 5)
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val dmem_resp_data = Bits(INPUT, fLen)
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val valid = Bool(INPUT)
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val fcsr_rdy = Bool(OUTPUT)
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val nack_mem = Bool(OUTPUT)
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val illegal_rm = Bool(OUTPUT)
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val killx = Bool(INPUT)
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val killm = Bool(INPUT)
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val dec = new FPUCtrlSigs().asOutput
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val sboard_set = Bool(OUTPUT)
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val sboard_clr = Bool(OUTPUT)
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val sboard_clra = UInt(OUTPUT, 5)
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}
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class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
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val cp_req = Decoupled(new FPInput()).flip //cp doesn't pay attn to kill sigs
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val cp_resp = Decoupled(new FPResult())
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}
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class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
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val data = Bits(width = fLen+1)
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val exc = Bits(width = 5)
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}
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class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
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val rm = Bits(width = 3)
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val typ = Bits(width = 2)
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val in1 = Bits(width = fLen+1)
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val in2 = Bits(width = fLen+1)
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val in3 = Bits(width = fLen+1)
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override def cloneType = new FPInput().asInstanceOf[this.type]
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}
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object ClassifyRecFN {
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def apply(expWidth: Int, sigWidth: Int, in: UInt) = {
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val sign = in(sigWidth + expWidth)
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val exp = in(sigWidth + expWidth - 1, sigWidth - 1)
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val sig = in(sigWidth - 2, 0)
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val code = exp(expWidth,expWidth-2)
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val codeHi = code(2, 1)
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val isSpecial = codeHi === UInt(3)
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val isHighSubnormalIn = exp(expWidth-2, 0) < UInt(2)
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val isSubnormal = code === UInt(1) || codeHi === UInt(1) && isHighSubnormalIn
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val isNormal = codeHi === UInt(1) && !isHighSubnormalIn || codeHi === UInt(2)
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val isZero = code === UInt(0)
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val isInf = isSpecial && !exp(expWidth-2)
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val isNaN = code.andR
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val isSNaN = isNaN && !sig(sigWidth-2)
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val isQNaN = isNaN && sig(sigWidth-2)
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Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
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isSubnormal && !sign, isZero && !sign, isZero && sign,
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isSubnormal && sign, isNormal && sign, isInf && sign)
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}
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}
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object IsNaNRecFN {
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def apply(in: UInt, t: FType) = in(t.sig + t.exp - 1, t.sig + t.exp - 3).andR
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}
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object IsSNaNRecFN {
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def apply(in: UInt, t: FType) = IsNaNRecFN(in, t) && !in(t.sig - 2)
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}
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class FType(val exp: Int, val sig: Int)
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object FType {
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val S = new FType(8, 24)
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val D = new FType(11, 53)
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}
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/** Format conversion without rounding or NaN handling */
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object RecFNToRecFN_noncompliant {
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def apply(in: UInt, inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) = {
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val sign = in(inSigWidth + inExpWidth)
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val fractIn = in(inSigWidth - 2, 0)
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val expIn = in(inSigWidth + inExpWidth - 1, inSigWidth - 1)
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val fractOut = fractIn << outSigWidth >> inSigWidth
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val expOut = {
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val expCode = expIn(inExpWidth, inExpWidth - 2)
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val commonCase = (expIn + (1 << outExpWidth)) - (1 << inExpWidth)
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Mux(expCode === 0 || expCode >= 6, Cat(expCode, commonCase(outExpWidth - 3, 0)),
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commonCase(outExpWidth, 0))
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}
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Cat(sign, expOut, fractOut)
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}
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}
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object CanonicalNaN {
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def apply(t: FType): UInt =
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UInt((BigInt(7) << (t.exp + t.sig - 3)) + (BigInt(1) << (t.sig - 2)), t.exp + t.sig + 1)
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def signaling(t: FType): UInt =
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UInt((BigInt(7) << (t.exp + t.sig - 3)) + (BigInt(1) << (t.sig - 3)), t.exp + t.sig + 1)
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}
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trait HasFPUParameters {
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val fLen: Int
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val (sExpWidth, sSigWidth) = (FType.S.exp, FType.S.sig)
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val (dExpWidth, dSigWidth) = (FType.D.exp, FType.D.sig)
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val floatTypes = fLen match {
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case 32 => List(FType.S)
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case 64 => List(FType.S, FType.D)
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}
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val maxType = floatTypes.sortWith(_.exp > _.exp).head
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val maxExpWidth = maxType.exp
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val maxSigWidth = maxType.sig
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def expand(x: UInt, t: FType) = RecFNToRecFN_noncompliant(x, t.exp, t.sig, maxType.exp, maxType.sig)
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def contract(x: UInt, t: FType) = RecFNToRecFN_noncompliant(x, maxType.exp, maxType.sig, t.exp, t.sig)
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}
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abstract class FPUModule(implicit p: Parameters) extends CoreModule()(p) with HasFPUParameters
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class FPToInt(implicit p: Parameters) extends FPUModule()(p) {
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class Output extends Bundle {
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val lt = Bool()
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val store = Bits(width = fLen)
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val toint = Bits(width = xLen)
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val exc = Bits(width = 5)
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override def cloneType = new Output().asInstanceOf[this.type]
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}
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val io = new Bundle {
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val in = Valid(new FPInput).flip
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val as_double = new FPInput().asOutput
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val out = Valid(new Output)
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}
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val in = RegEnable(io.in.bits, io.in.valid)
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val valid = Reg(next=io.in.valid)
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val in1_s = contract(in.in1, FType.S)
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val unrec_s = hardfloat.fNFromRecFN(sExpWidth, sSigWidth, in1_s).sextTo(xLen)
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val unrec_mem = fLen match {
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case 32 => unrec_s
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case 64 =>
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val unrec_d = hardfloat.fNFromRecFN(dExpWidth, dSigWidth, in.in1).sextTo(xLen)
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Mux(in.single, unrec_s, unrec_d)
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}
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val unrec_int = xLen match {
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case 32 => unrec_s
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case fLen => unrec_mem
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}
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val classify_s = ClassifyRecFN(sExpWidth, sSigWidth, in1_s)
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val classify_out = fLen match {
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case 32 => classify_s
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case 64 =>
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val classify_d = ClassifyRecFN(dExpWidth, dSigWidth, in.in1)
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Mux(in.single, classify_s, classify_d)
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}
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val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
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dcmp.io.a := in.in1
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dcmp.io.b := in.in2
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dcmp.io.signaling := !in.rm(1)
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io.out.bits.toint := Mux(in.rm(0), classify_out, unrec_int)
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io.out.bits.store := unrec_mem
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io.out.bits.exc := Bits(0)
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when (in.cmd === FCMD_CMP) {
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io.out.bits.toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR
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io.out.bits.exc := dcmp.io.exceptionFlags
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}
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when (in.cmd === FCMD_CVT_IF) {
|
|
val minXLen = 32
|
|
val n = log2Ceil(xLen/minXLen) + 1
|
|
for (i <- 0 until n) {
|
|
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, minXLen << i))
|
|
conv.io.in := in.in1
|
|
conv.io.roundingMode := in.rm
|
|
conv.io.signedOut := ~in.typ(0)
|
|
when (in.typ.extract(log2Ceil(n), 1) === i) {
|
|
io.out.bits.toint := conv.io.out.sextTo(xLen)
|
|
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, UInt(0, 3), conv.io.intExceptionFlags(0))
|
|
}
|
|
}
|
|
}
|
|
|
|
io.out.valid := valid
|
|
io.out.bits.lt := dcmp.io.lt
|
|
io.as_double := in
|
|
}
|
|
|
|
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
|
|
val io = new Bundle {
|
|
val in = Valid(new FPInput).flip
|
|
val out = Valid(new FPResult)
|
|
}
|
|
|
|
val in = Pipe(io.in)
|
|
|
|
val mux = Wire(new FPResult)
|
|
mux.exc := Bits(0)
|
|
mux.data := expand(hardfloat.recFNFromFN(sExpWidth, sSigWidth, in.bits.in1), FType.S)
|
|
if (fLen > 32) when (!in.bits.single) {
|
|
mux.data := hardfloat.recFNFromFN(dExpWidth, dSigWidth, in.bits.in1)
|
|
}
|
|
|
|
val intValue = {
|
|
val minXLen = 32
|
|
val n = log2Ceil(xLen/minXLen) + 1
|
|
val res = Wire(init = in.bits.in1.asSInt)
|
|
for (i <- 0 until n-1) {
|
|
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
|
|
when (in.bits.typ.extract(log2Ceil(n), 1) === i) {
|
|
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
|
|
}
|
|
}
|
|
res.asUInt
|
|
}
|
|
|
|
when (in.bits.cmd === FCMD_CVT_FI) {
|
|
val l2s = Module(new hardfloat.INToRecFN(xLen, sExpWidth, sSigWidth))
|
|
l2s.io.signedIn := ~in.bits.typ(0)
|
|
l2s.io.in := intValue
|
|
l2s.io.roundingMode := in.bits.rm
|
|
mux.data := expand(l2s.io.out, FType.S)
|
|
mux.exc := l2s.io.exceptionFlags
|
|
|
|
fLen match {
|
|
case 32 =>
|
|
case 64 =>
|
|
val l2d = Module(new hardfloat.INToRecFN(xLen, dExpWidth, dSigWidth))
|
|
l2d.io.signedIn := ~in.bits.typ(0)
|
|
l2d.io.in := intValue
|
|
l2d.io.roundingMode := in.bits.rm
|
|
when (!in.bits.single) {
|
|
mux.data := l2d.io.out
|
|
mux.exc := l2d.io.exceptionFlags
|
|
}
|
|
}
|
|
}
|
|
|
|
io.out <> Pipe(in.valid, mux, latency-1)
|
|
}
|
|
|
|
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
|
|
val io = new Bundle {
|
|
val in = Valid(new FPInput).flip
|
|
val out = Valid(new FPResult)
|
|
val lt = Bool(INPUT) // from FPToInt
|
|
}
|
|
|
|
val in = Pipe(io.in)
|
|
|
|
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
|
|
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
|
|
|
|
val mux = Wire(new FPResult)
|
|
mux.exc := UInt(0)
|
|
mux.data := fsgnj
|
|
|
|
when (in.bits.cmd === FCMD_MINMAX) {
|
|
val isnan1 = IsNaNRecFN(in.bits.in1, maxType)
|
|
val isnan2 = IsNaNRecFN(in.bits.in2, maxType)
|
|
val isInvalid = IsSNaNRecFN(in.bits.in1, maxType) || IsSNaNRecFN(in.bits.in2, maxType)
|
|
val isNaNOut = isInvalid || (isnan1 && isnan2)
|
|
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
|
|
mux.exc := isInvalid << 4
|
|
mux.data := Mux(isNaNOut, CanonicalNaN(maxType), Mux(isLHS, in.bits.in1, in.bits.in2))
|
|
}
|
|
|
|
fLen match {
|
|
case 32 =>
|
|
case 64 =>
|
|
when (in.bits.cmd === FCMD_CVT_FF) {
|
|
val d2s = Module(new hardfloat.RecFNToRecFN(dExpWidth, dSigWidth, sExpWidth, sSigWidth))
|
|
d2s.io.in := in.bits.in1
|
|
d2s.io.roundingMode := in.bits.rm
|
|
|
|
val s2d = Module(new hardfloat.RecFNToRecFN(sExpWidth, sSigWidth, dExpWidth, dSigWidth))
|
|
s2d.io.in := contract(in.bits.in1, FType.S)
|
|
s2d.io.roundingMode := in.bits.rm
|
|
|
|
when (in.bits.single) {
|
|
mux.data := expand(d2s.io.out, FType.S)
|
|
mux.exc := d2s.io.exceptionFlags
|
|
}.otherwise {
|
|
mux.data := s2d.io.out
|
|
mux.exc := s2d.io.exceptionFlags
|
|
}
|
|
}
|
|
}
|
|
|
|
io.out <> Pipe(in.valid, mux, latency-1)
|
|
}
|
|
|
|
class FPUFMAPipe(val latency: Int, t: FType)(implicit p: Parameters) extends FPUModule()(p) {
|
|
val io = new Bundle {
|
|
val in = Valid(new FPInput).flip
|
|
val out = Valid(new FPResult)
|
|
}
|
|
|
|
val width = t.sig + t.exp
|
|
val one = UInt(1) << (width-1)
|
|
val zero = (io.in.bits.in1(width) ^ io.in.bits.in2(width)) << width
|
|
|
|
val valid = Reg(next=io.in.valid)
|
|
val in = Reg(new FPInput)
|
|
when (io.in.valid) {
|
|
val cmd_fma = io.in.bits.ren3
|
|
val cmd_addsub = io.in.bits.swap23
|
|
in := io.in.bits
|
|
in.in1 := contract(io.in.bits.in1, t)
|
|
in.in2 := Mux(cmd_addsub, one, contract(io.in.bits.in2, t))
|
|
in.in3 := Mux(cmd_fma || cmd_addsub, contract(io.in.bits.in3, t), zero)
|
|
in.cmd := Cat(io.in.bits.cmd(1) & (cmd_fma || cmd_addsub), io.in.bits.cmd(0))
|
|
}
|
|
|
|
val fma = Module(new hardfloat.MulAddRecFN(t.exp, t.sig))
|
|
fma.io.op := in.cmd
|
|
fma.io.roundingMode := in.rm
|
|
fma.io.a := in.in1
|
|
fma.io.b := in.in2
|
|
fma.io.c := in.in3
|
|
|
|
val res = Wire(new FPResult)
|
|
res.data := expand(fma.io.out, t)
|
|
res.exc := fma.io.exceptionFlags
|
|
io.out := Pipe(valid, res, latency-1)
|
|
}
|
|
|
|
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
|
|
val io = new FPUIO
|
|
|
|
val ex_reg_valid = Reg(next=io.valid, init=Bool(false))
|
|
val req_valid = ex_reg_valid || io.cp_req.valid
|
|
val ex_reg_inst = RegEnable(io.inst, io.valid)
|
|
val ex_cp_valid = io.cp_req.fire()
|
|
val mem_reg_valid = Reg(next=ex_reg_valid && !io.killx || ex_cp_valid, init=Bool(false))
|
|
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
|
|
val mem_cp_valid = Reg(next=ex_cp_valid, init=Bool(false))
|
|
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
|
|
val wb_reg_valid = Reg(next=mem_reg_valid && (!killm || mem_cp_valid), init=Bool(false))
|
|
val wb_cp_valid = Reg(next=mem_cp_valid, init=Bool(false))
|
|
|
|
val fp_decoder = Module(new FPUDecoder)
|
|
fp_decoder.io.inst := io.inst
|
|
|
|
val cp_ctrl = Wire(new FPUCtrlSigs)
|
|
cp_ctrl <> io.cp_req.bits
|
|
io.cp_resp.valid := Bool(false)
|
|
io.cp_resp.bits.data := UInt(0)
|
|
|
|
val id_ctrl = fp_decoder.io.sigs
|
|
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, RegEnable(id_ctrl, io.valid))
|
|
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
|
|
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
|
|
|
|
// load response
|
|
val load_wb = Reg(next=io.dmem_resp_val)
|
|
val load_wb_single = RegEnable(!io.dmem_resp_type(0), io.dmem_resp_val)
|
|
val load_wb_data = RegEnable(io.dmem_resp_data, io.dmem_resp_val)
|
|
val load_wb_tag = RegEnable(io.dmem_resp_tag, io.dmem_resp_val)
|
|
val rec_s = hardfloat.recFNFromFN(sExpWidth, sSigWidth, load_wb_data)
|
|
val load_wb_data_recoded = fLen match {
|
|
case 32 => rec_s
|
|
case 64 =>
|
|
val rec_d = hardfloat.recFNFromFN(dExpWidth, dSigWidth, load_wb_data)
|
|
Mux(load_wb_single, expand(rec_s, FType.S), rec_d)
|
|
}
|
|
|
|
// regfile
|
|
val regfile = Mem(32, Bits(width = fLen+1))
|
|
when (load_wb) {
|
|
regfile(load_wb_tag) := load_wb_data_recoded
|
|
if (enableCommitLog)
|
|
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32, Mux(load_wb_single, load_wb_data(31,0), load_wb_data))
|
|
}
|
|
|
|
val ex_ra1::ex_ra2::ex_ra3::Nil = List.fill(3)(Reg(UInt()))
|
|
when (io.valid) {
|
|
when (id_ctrl.ren1) {
|
|
when (!id_ctrl.swap12) { ex_ra1 := io.inst(19,15) }
|
|
when (id_ctrl.swap12) { ex_ra2 := io.inst(19,15) }
|
|
}
|
|
when (id_ctrl.ren2) {
|
|
when (id_ctrl.swap12) { ex_ra1 := io.inst(24,20) }
|
|
when (id_ctrl.swap23) { ex_ra3 := io.inst(24,20) }
|
|
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra2 := io.inst(24,20) }
|
|
}
|
|
when (id_ctrl.ren3) { ex_ra3 := io.inst(31,27) }
|
|
}
|
|
val ex_rm = Mux(ex_reg_inst(14,12) === Bits(7), io.fcsr_rm, ex_reg_inst(14,12))
|
|
|
|
val req = Wire(new FPInput)
|
|
req := ex_ctrl
|
|
req.rm := ex_rm
|
|
req.in1 := regfile(ex_ra1)
|
|
req.in2 := regfile(ex_ra2)
|
|
req.in3 := regfile(ex_ra3)
|
|
req.typ := ex_reg_inst(21,20)
|
|
when (ex_cp_valid) {
|
|
req := io.cp_req.bits
|
|
when (io.cp_req.bits.swap23) {
|
|
req.in2 := io.cp_req.bits.in3
|
|
req.in3 := io.cp_req.bits.in2
|
|
}
|
|
}
|
|
|
|
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
|
|
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.single
|
|
sfma.io.in.bits := req
|
|
|
|
val fpiu = Module(new FPToInt)
|
|
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || ex_ctrl.cmd === FCMD_MINMAX)
|
|
fpiu.io.in.bits := req
|
|
io.store_data := fpiu.io.out.bits.store
|
|
io.toint_data := fpiu.io.out.bits.toint
|
|
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
|
|
io.cp_resp.bits.data := fpiu.io.out.bits.toint
|
|
io.cp_resp.valid := Bool(true)
|
|
}
|
|
|
|
val ifpu = Module(new IntToFP(2))
|
|
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
|
|
ifpu.io.in.bits := req
|
|
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
|
|
|
|
val fpmu = Module(new FPToFP(2))
|
|
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
|
|
fpmu.io.in.bits := req
|
|
fpmu.io.lt := fpiu.io.out.bits.lt
|
|
|
|
val divSqrt_wen = Reg(next=Bool(false))
|
|
val divSqrt_inReady = Wire(init=Bool(false))
|
|
val divSqrt_waddr = Reg(UInt(width = 5))
|
|
val divSqrt_single = Reg(Bool())
|
|
val divSqrt_wdata = Wire(UInt(width = fLen+1))
|
|
val divSqrt_flags = Wire(UInt(width = 5))
|
|
val divSqrt_in_flight = Reg(init=Bool(false))
|
|
val divSqrt_killed = Reg(Bool())
|
|
|
|
// writeback arbitration
|
|
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
|
|
val pipes = List(
|
|
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
|
|
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
|
|
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.single, sfma.io.out.bits)) ++
|
|
(fLen > 32).option({
|
|
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
|
|
dfma.io.in.valid := req_valid && ex_ctrl.fma && !ex_ctrl.single
|
|
dfma.io.in.bits := req
|
|
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && !c.single, dfma.io.out.bits)
|
|
})
|
|
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
|
|
require(pipes.forall(_.lat >= offset))
|
|
pipes.map(p => Mux(p.cond(c), UInt(1 << p.lat-offset), UInt(0))).reduce(_|_)
|
|
}
|
|
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), UInt(p._2), UInt(0))).reduce(_|_)
|
|
val maxLatency = pipes.map(_.lat).max
|
|
val memLatencyMask = latencyMask(mem_ctrl, 2)
|
|
|
|
class WBInfo extends Bundle {
|
|
val rd = UInt(width = 5)
|
|
val single = Bool()
|
|
val cp = Bool()
|
|
val pipeid = UInt(width = log2Ceil(pipes.size))
|
|
override def cloneType: this.type = new WBInfo().asInstanceOf[this.type]
|
|
}
|
|
|
|
val wen = Reg(init=Bits(0, maxLatency-1))
|
|
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
|
|
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
|
|
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
|
|
|
|
for (i <- 0 until maxLatency-2) {
|
|
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
|
|
}
|
|
wen := wen >> 1
|
|
when (mem_wen) {
|
|
when (!killm) {
|
|
wen := wen >> 1 | memLatencyMask
|
|
}
|
|
for (i <- 0 until maxLatency-1) {
|
|
when (!write_port_busy && memLatencyMask(i)) {
|
|
wbInfo(i).cp := mem_cp_valid
|
|
wbInfo(i).single := mem_ctrl.single
|
|
wbInfo(i).pipeid := pipeid(mem_ctrl)
|
|
wbInfo(i).rd := mem_reg_inst(11,7)
|
|
}
|
|
}
|
|
}
|
|
|
|
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
|
|
val wdata = Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid))
|
|
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
|
|
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
|
|
regfile(waddr) := wdata
|
|
if (enableCommitLog) {
|
|
val wsingle = Mux(divSqrt_wen, divSqrt_single, wbInfo(0).single)
|
|
val wdata_unrec_s = hardfloat.fNFromRecFN(sExpWidth, sSigWidth, contract(wdata, FType.S))
|
|
val unrec = fLen match {
|
|
case 32 => wdata_unrec_s
|
|
case 64 =>
|
|
val wdata_unrec_d = hardfloat.fNFromRecFN(dExpWidth, dSigWidth, wdata)
|
|
Mux(wsingle, wdata_unrec_s, wdata_unrec_d)
|
|
}
|
|
printf("f%d p%d 0x%x\n", waddr, waddr + 32, unrec)
|
|
}
|
|
}
|
|
when (wbInfo(0).cp && wen(0)) {
|
|
io.cp_resp.bits.data := wdata
|
|
io.cp_resp.valid := Bool(true)
|
|
}
|
|
io.cp_req.ready := !ex_reg_valid
|
|
|
|
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
|
|
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
|
|
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
|
|
io.fcsr_flags.bits :=
|
|
Mux(wb_toint_valid, wb_toint_exc, UInt(0)) |
|
|
Mux(divSqrt_wen, divSqrt_flags, UInt(0)) |
|
|
Mux(wen(0), wexc, UInt(0))
|
|
|
|
val units_busy = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && (!divSqrt_inReady || wen.orR)
|
|
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_in_flight)
|
|
io.nack_mem := units_busy || write_port_busy || divSqrt_in_flight
|
|
io.dec <> fp_decoder.io.sigs
|
|
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(Bool(false))(_||_)
|
|
io.sboard_set := wb_reg_valid && !wb_cp_valid && Reg(next=useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt)
|
|
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === UInt(x._2))))
|
|
io.sboard_clra := waddr
|
|
// we don't currently support round-max-magnitude (rm=4)
|
|
io.illegal_rm := io.inst(14,12).isOneOf(5, 6) || io.inst(14,12) === 7 && io.fcsr_rm >= 5
|
|
|
|
divSqrt_wdata := 0
|
|
divSqrt_flags := 0
|
|
if (cfg.divSqrt) {
|
|
require(fLen == 64)
|
|
val divSqrt_rm = Reg(Bits())
|
|
val divSqrt_flags_double = Reg(Bits())
|
|
val divSqrt_wdata_double = Reg(Bits())
|
|
|
|
val divSqrt = Module(new hardfloat.DivSqrtRecF64)
|
|
divSqrt_inReady := Mux(divSqrt.io.sqrtOp, divSqrt.io.inReady_sqrt, divSqrt.io.inReady_div)
|
|
val divSqrt_outValid = divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt
|
|
divSqrt.io.inValid := mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_in_flight
|
|
divSqrt.io.sqrtOp := mem_ctrl.sqrt
|
|
divSqrt.io.a := fpiu.io.as_double.in1
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divSqrt.io.b := fpiu.io.as_double.in2
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|
divSqrt.io.roundingMode := fpiu.io.as_double.rm
|
|
|
|
when (divSqrt.io.inValid && divSqrt_inReady) {
|
|
divSqrt_in_flight := true
|
|
divSqrt_killed := killm
|
|
divSqrt_single := mem_ctrl.single
|
|
divSqrt_waddr := mem_reg_inst(11,7)
|
|
divSqrt_rm := divSqrt.io.roundingMode
|
|
}
|
|
|
|
when (divSqrt_outValid) {
|
|
divSqrt_wen := !divSqrt_killed
|
|
divSqrt_wdata_double := divSqrt.io.out
|
|
divSqrt_in_flight := false
|
|
divSqrt_flags_double := divSqrt.io.exceptionFlags
|
|
}
|
|
|
|
val divSqrt_toSingle = Module(new hardfloat.RecFNToRecFN(11, 53, 8, 24))
|
|
divSqrt_toSingle.io.in := divSqrt_wdata_double
|
|
divSqrt_toSingle.io.roundingMode := divSqrt_rm
|
|
divSqrt_wdata := Mux(divSqrt_single, expand(divSqrt_toSingle.io.out, FType.S), divSqrt_wdata_double)
|
|
divSqrt_flags := divSqrt_flags_double | Mux(divSqrt_single, divSqrt_toSingle.io.exceptionFlags, Bits(0))
|
|
} else {
|
|
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true }
|
|
}
|
|
}
|
|
|
|
/** Mix-ins for constructing tiles that may have an FPU external to the core pipeline */
|
|
trait CanHaveSharedFPU extends HasTileParameters
|
|
|
|
trait CanHaveSharedFPUModule {
|
|
val outer: CanHaveSharedFPU
|
|
val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new FPU(params)(outer.p)))
|
|
// TODO fpArb could go here instead of inside LegacyRoccComplex
|
|
}
|