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coreplex: CacheBlockOffsetBits was wrong!

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This bug is ancient. I don't understand how it never mattered before.
Anyway, in processors with a custom CacheBlockBytes, this value is wrong!
The symptom is that TL1 components end up missing high address bits.
This causes, for example, a system to jump to 0 instead of RAM.

I don't understand how this very serious bug did not cause problems before.
This commit is contained in:
Wesley W. Terpstra 2016-11-24 15:50:49 -08:00 committed by Andrew Waterman
parent 549e006988
commit 0baa1c9a45
1 changed files with 1 additions and 1 deletions
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src/main/scala/coreplex/Configs.scala
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@ -109,7 +109,7 @@ class BaseCoreplexConfig extends Config (
case BroadcastConfig => BroadcastConfig() case BroadcastConfig => BroadcastConfig()
case BankedL2Config => BankedL2Config() case BankedL2Config => BankedL2Config()
case CacheBlockBytes => 64 case CacheBlockBytes => 64
case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes)) case CacheBlockOffsetBits => log2Up(site(CacheBlockBytes))
case EnableL2Logging => false case EnableL2Logging => false
case _ => throw new CDEMatchError case _ => throw new CDEMatchError
} }