From 0baa1c9a45eb10fcfa789a9ff99d1fbbb2e29b11 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 24 Nov 2016 15:50:49 -0800 Subject: [PATCH] coreplex: CacheBlockOffsetBits was wrong! This bug is ancient. I don't understand how it never mattered before. Anyway, in processors with a custom CacheBlockBytes, this value is wrong! The symptom is that TL1 components end up missing high address bits. This causes, for example, a system to jump to 0 instead of RAM. I don't understand how this very serious bug did not cause problems before. --- src/main/scala/coreplex/Configs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index 71cd5434..ff6e8946 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -109,7 +109,7 @@ class BaseCoreplexConfig extends Config ( case BroadcastConfig => BroadcastConfig() case BankedL2Config => BankedL2Config() case CacheBlockBytes => 64 - case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes)) + case CacheBlockOffsetBits => log2Up(site(CacheBlockBytes)) case EnableL2Logging => false case _ => throw new CDEMatchError }