riscv/rocket-chip
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WritebackUnit multibeat control logic bugfix

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This commit is contained in:
Henry Cook 2015-02-16 10:59:57 -08:00
parent aa46b8b72d
commit 0b131173e6
1 changed files with 2 additions and 1 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -418,7 +418,8 @@ class WritebackUnit extends L1HellaCacheModule {
data_req_cnt := data_req_cnt - Mux[UInt](Bool(refillCycles > 1) && r1_data_req_fired, 2, 1) data_req_cnt := data_req_cnt - Mux[UInt](Bool(refillCycles > 1) && r1_data_req_fired, 2, 1)
} .elsewhen(beat_done) { if(refillCyclesPerBeat > 1) buf_v := 0 } } .elsewhen(beat_done) { if(refillCyclesPerBeat > 1) buf_v := 0 }
when(!r1_data_req_fired) { when(!r1_data_req_fired) {
active := data_req_cnt < UInt(refillCycles) // We're done if this is the final data request and the Release can be sent
active := data_req_cnt < UInt(refillCycles) || !io.release.ready
} }
} }
} }