rocketchip: bundle (=> B) need not be delayed; Module is constructed later

src/main/scala/coreplex/BaseCoreplex.scala

@@ -76,7 +76,7 @@ abstract class BaseCoreplexBundle(val c: CoreplexConfig)(implicit val p: Paramet
 }
 
 abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
-    c: CoreplexConfig, l: L, b: => B)(implicit val p: Parameters) extends LazyModuleImp(l) with HasCoreplexParameters {
+    c: CoreplexConfig, l: L, b: B)(implicit val p: Parameters) extends LazyModuleImp(l) with HasCoreplexParameters {
   val outer: L = l
   val io: B = b
 

src/main/scala/coreplex/Coreplex.scala

@@ -34,7 +34,7 @@ class DefaultCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCor
 class DefaultCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
 
 class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle](
-    c: CoreplexConfig, l: L, b: => B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
+    c: CoreplexConfig, l: L, b: B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
     with DirectConnection
 
 /////
@@ -81,5 +81,5 @@ class MultiClockCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extend
     with TileClockResetBundle
 
 class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle](
-    c: CoreplexConfig, l: L, b: => B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
+    c: CoreplexConfig, l: L, b: B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
     with AsyncConnection

src/main/scala/groundtest/Coreplex.scala

@@ -11,6 +11,6 @@ class GroundTestCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends Base
 class GroundTestCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
 
 class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle](
-    c: CoreplexConfig, l: L, b: => B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p) with DirectConnection {
+    c: CoreplexConfig, l: L, b: B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p) with DirectConnection {
   io.success := tiles.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
 }

src/main/scala/rocketchip/BaseTop.scala

@@ -72,10 +72,9 @@ abstract class BaseTopBundle(val p: Parameters) extends Bundle {
 }
 
 abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](
-    val p: Parameters, l: L, b: => B) extends LazyModuleImp(l) {
+    val p: Parameters,
-  val outer: L = l
+    val outer: L,
-  val io: B = b
+    val io: B) extends LazyModuleImp(outer) {
-
   val coreplex = p(BuildCoreplex)(outer.c, p)
   val coreplexIO = Wire(coreplex.io)
 

src/main/scala/rocketchip/ExampleTop.scala

@@ -29,7 +29,7 @@ class ExampleTopBundle(p: Parameters) extends BaseTopBundle(p)
     with PeripheryMasterMMIOBundle
     with PeripherySlaveBundle
 
-class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: => B) extends BaseTopModule(p, l, b)
+class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: B) extends BaseTopModule(p, l, b)
     with PeripheryBootROMModule
     with PeripheryDebugModule
     with PeripheryExtInterruptsModule
@@ -49,5 +49,5 @@ class ExampleTopWithTestRAM(q: Parameters) extends ExampleTop(q)
 class ExampleTopWithTestRAMBundle(p: Parameters) extends ExampleTopBundle(p)
     with PeripheryTestRAMBundle
 
-class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle](p: Parameters, l: L, b: => B) extends ExampleTopModule(p, l, b)
+class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle](p: Parameters, l: L, b: B) extends ExampleTopModule(p, l, b)
     with PeripheryTestRAMModule