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compute number of outstanding misses for DRAMSideLLCNull

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This commit is contained in:
Yunsup Lee 2014-09-12 18:06:20 -07:00
parent e40a6fdd64
commit 09de2e2794
1 changed files with 1 additions and 1 deletions
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src/main/scala/PublicConfigs.scala
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@ -108,7 +108,7 @@ class DefaultConfig extends ChiselConfig {
Module(new DRAMSideLLC_HasKnownBug(sets=512, ways=8, outstanding=16, Module(new DRAMSideLLC_HasKnownBug(sets=512, ways=8, outstanding=16,
refill_cycles=refill, tagLeaf=tag, dataLeaf=data)) refill_cycles=refill, tagLeaf=tag, dataLeaf=data))
} else { } else {
Module(new DRAMSideLLCNull(8, refill)) Module(new DRAMSideLLCNull(site(NReleaseTransactors)+site(NAcquireTransactors), refill))
} }
} }
case BuildCoherenceMaster => (id: Int) => { case BuildCoherenceMaster => (id: Int) => {