From 0866b4c0452d25b6556f0e46e931ebb39ac2a718 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Wed, 1 Jun 2016 23:36:34 -0700
Subject: [PATCH] Can't assign to Vec literals

---
 uncore/src/main/scala/debug.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/uncore/src/main/scala/debug.scala b/uncore/src/main/scala/debug.scala
index 4cb24eb5..a2f16360 100644
--- a/uncore/src/main/scala/debug.scala
+++ b/uncore/src/main/scala/debug.scala
@@ -593,7 +593,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
   sbRamWrData := sbWrData
 
   require (dbRamAddrWidth >= ramAddrWidth)    // SB accesses less than 32 bits Not Implemented.
-  val dbRamWrMask = Vec.fill(1 << (dbRamAddrWidth - ramAddrWidth)){Fill(dbRamDataWidth, UInt(1, width=1))}
+  val dbRamWrMask = Wire(init=Vec.fill(1 << (dbRamAddrWidth - ramAddrWidth)){Fill(dbRamDataWidth, UInt(1, width=1))})
 
   if (dbRamDataWidth < ramDataWidth){