riscv/rocket-chip
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Removed sret from ptw; sret now comes thru io.cpu to dcache

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This commit is contained in:
Christopher Celio
2015-03-03 16:50:41 -08:00
parent 5d07733057
commit 06dea3790a
4 changed files with 3 additions and 5 deletions
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3
rocket/src/main/scala/nbdcache.scala
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@ -83,6 +83,7 @@ class HellaCacheIO extends CoreBundle {
val resp = Valid(new HellaCacheResp).flip
val replay_next = Valid(Bits(width = coreDCacheReqTagBits)).flip
val xcpt = (new HellaCacheExceptions).asInput
val sret = Bool(OUTPUT)
val ordered = Bool(INPUT)
}
@ -750,7 +751,7 @@ class HellaCache extends L1HellaCacheModule {
lrsc_count := 0
}
}
when (io.ptw.sret) { lrsc_count := 0 }
when (io.cpu.sret) { lrsc_count := 0 }
val s2_data = Vec.fill(nWays){Bits(width = encRowBits)}
for (w <- 0 until nWays) {