Removed sret from ptw; sret now comes thru io.cpu to dcache

2015-03-03 16:50:41 -08:00
parent 5d07733057
commit 06dea3790a
4 changed files with 3 additions and 5 deletions
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@ -675,6 +675,7 @@ class Control extends CoreModule
  io.dmem.req.bits.cmd  := ex_ctrl.mem_cmd
  io.dmem.req.bits.typ  := ex_ctrl.mem_type
  io.dmem.req.bits.phys := Bool(false)
+  io.dmem.sret          := io.dpath.sret

  io.rocc.cmd.valid := wb_rocc_val
  io.rocc.exception := wb_reg_xcpt && sr.er