From 05d311c517105a75d0ff113353d2971cb5716439 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 27 Aug 2015 09:47:02 -0700 Subject: [PATCH] Use Vec.apply, not Vec.fill, for type nodes --- uncore/src/main/scala/broadcast.scala | 8 ++++---- uncore/src/main/scala/cache.scala | 16 ++++++++-------- uncore/src/main/scala/htif.scala | 4 ++-- uncore/src/main/scala/network.scala | 6 +++--- uncore/src/main/scala/tilelink.scala | 12 ++++++------ uncore/src/main/scala/uncore.scala | 2 +- uncore/src/main/scala/util.scala | 2 +- 7 files changed, 25 insertions(+), 25 deletions(-) diff --git a/uncore/src/main/scala/broadcast.scala b/uncore/src/main/scala/broadcast.scala index 620c4bd2..9f6aba6e 100644 --- a/uncore/src/main/scala/broadcast.scala +++ b/uncore/src/main/scala/broadcast.scala @@ -40,7 +40,7 @@ class L2BroadcastHub extends ManagerCoherenceAgent trackerList.map(_.io.incoherent := io.incoherent) // Queue to store impending Put data - val sdq = Reg(Vec.fill(sdqDepth){io.iacq().data}) + val sdq = Reg(Vec(io.iacq().data, sdqDepth)) val sdq_val = Reg(init=Bits(0, sdqDepth)) val sdq_alloc_id = PriorityEncoder(~sdq_val) val sdq_rdy = !sdq_val.andR @@ -69,7 +69,7 @@ class L2BroadcastHub extends ManagerCoherenceAgent val voluntary = io.irel().isVoluntary() val vwbdq_enq = io.inner.release.fire() && voluntary && io.irel().hasData() val (rel_data_cnt, rel_data_done) = Counter(vwbdq_enq, innerDataBeats) //TODO Zero width - val vwbdq = Reg(Vec.fill(innerDataBeats){io.irel().data}) //TODO Assumes nReleaseTransactors == 1 + val vwbdq = Reg(Vec(io.irel().data, innerDataBeats)) //TODO Assumes nReleaseTransactors == 1 when(vwbdq_enq) { vwbdq(rel_data_cnt) := io.irel().data } // Handle releases, which might be voluntary and might have data @@ -131,7 +131,7 @@ class BroadcastVoluntaryReleaseTracker(trackerId: Int) extends BroadcastXactTrac val state = Reg(init=s_idle) val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 })) - val data_buffer = Reg(Vec.fill(innerDataBeats){io.irel().data}) + val data_buffer = Reg(Vec(io.irel().data, innerDataBeats)) val coh = ManagerMetadata.onReset val collect_irel_data = Reg(init=Bool(false)) @@ -210,7 +210,7 @@ class BroadcastAcquireTracker(trackerId: Int) extends BroadcastXactTracker { val state = Reg(init=s_idle) val xact = Reg(Bundle(new AcquireFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 })) - val data_buffer = Reg(Vec.fill(innerDataBeats){io.iacq().data}) + val data_buffer = Reg(Vec(io.iacq().data, innerDataBeats)) val coh = ManagerMetadata.onReset assert(!(state != s_idle && xact.isBuiltInType() && diff --git a/uncore/src/main/scala/cache.scala b/uncore/src/main/scala/cache.scala index 64966c20..30168286 100644 --- a/uncore/src/main/scala/cache.scala +++ b/uncore/src/main/scala/cache.scala @@ -145,7 +145,7 @@ class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule { val io = new Bundle { val read = Decoupled(new MetaReadReq).flip val write = Decoupled(new MetaWriteReq(rstVal)).flip - val resp = Vec.fill(nWays){rstVal.cloneType.asOutput} + val resp = Vec(rstVal.cloneType.asOutput, nWays) } val rst_cnt = Reg(init=UInt(0, log2Up(nSets+1))) val rst = rst_cnt < UInt(nSets) @@ -427,9 +427,9 @@ abstract class L2XactTracker extends XactTracker with L2HellaCacheParameters { class CacheBlockBuffer { // TODO val buffer = Reg(Bits(width = params(CacheBlockBytes)*8)) - def internal = Vec.fill(internalDataBeats){ Bits(width = rowBits) }.fromBits(buffer) - def inner = Vec.fill(innerDataBeats){ Bits(width = innerDataBits) }.fromBits(buffer) - def outer = Vec.fill(outerDataBeats){ Bits(width = outerDataBits) }.fromBits(buffer) + def internal = Vec(Bits(width = rowBits), internalDataBeats).fromBits(buffer) + def inner = Vec(Bits(width = innerDataBits), innerDataBeats).fromBits(buffer) + def outer = Vec(Bits(width = outerDataBits), outerDataBeats).fromBits(buffer) } def connectDataBeatCounter[S <: L2HellaCacheBundle](inc: Bool, data: S, beat: UInt, full_block: Bool) = { @@ -492,7 +492,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int) extends L2XactTracker { val state = Reg(init=s_idle) val xact = Reg(Bundle(new ReleaseFromSrc, { case TLId => params(InnerTLId); case TLDataBits => 0 })) - val data_buffer = Reg(init=Vec.fill(innerDataBeats){UInt(0, width = innerDataBits)}) + val data_buffer = Reg(init=Vec(UInt(0, width = innerDataBits), innerDataBeats)) val xact_way_en = Reg{ Bits(width = nWays) } val xact_old_meta = Reg{ new L2Metadata } val coh = xact_old_meta.coh @@ -587,8 +587,8 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker { // State holding transaction metadata val xact = Reg(Bundle(new AcquireFromSrc, { case TLId => params(InnerTLId) })) - val data_buffer = Reg(init=Vec.fill(innerDataBeats){UInt(0, width = innerDataBits)}) - val wmask_buffer = Reg(init=Vec.fill(innerDataBeats){UInt(0, width = innerDataBits/8)}) + val data_buffer = Reg(init=Vec(UInt(0, width = innerDataBits), innerDataBeats)) + val wmask_buffer = Reg(init=Vec(UInt(0, width = innerDataBits/8), innerDataBeats)) val xact_tag_match = Reg{ Bool() } val xact_way_en = Reg{ Bits(width = nWays) } val xact_old_meta = Reg{ new L2Metadata } @@ -980,7 +980,7 @@ class L2WritebackUnit(trackerId: Int) extends L2XactTracker { val state = Reg(init=s_idle) val xact = Reg(new L2WritebackReq) - val data_buffer = Reg(init=Vec.fill(innerDataBeats){UInt(0, width = innerDataBits)}) + val data_buffer = Reg(init=Vec(UInt(0, width = innerDataBits), innerDataBeats)) val xact_addr_block = Cat(xact.tag, xact.idx) val pending_irels = diff --git a/uncore/src/main/scala/htif.scala b/uncore/src/main/scala/htif.scala index 8aeba790..d162be98 100644 --- a/uncore/src/main/scala/htif.scala +++ b/uncore/src/main/scala/htif.scala @@ -51,7 +51,7 @@ class HTIFIO extends HTIFBundle { } class SCRIO extends HTIFBundle { - val rdata = Vec.fill(nSCR){Bits(INPUT, 64)} + val rdata = Vec(Bits(INPUT, 64), nSCR) val wen = Bool(OUTPUT) val waddr = UInt(OUTPUT, log2Up(nSCR)) val wdata = Bits(OUTPUT, 64) @@ -59,7 +59,7 @@ class SCRIO extends HTIFBundle { class HTIFModuleIO extends HTIFBundle { val host = new HostIO - val cpu = Vec.fill(nCores){new HTIFIO}.flip + val cpu = Vec(new HTIFIO, nCores).flip val mem = new ClientUncachedTileLinkIO val scr = new SCRIO } diff --git a/uncore/src/main/scala/network.scala b/uncore/src/main/scala/network.scala index ccb6c593..16d2c1e7 100644 --- a/uncore/src/main/scala/network.scala +++ b/uncore/src/main/scala/network.scala @@ -18,8 +18,8 @@ class PhysicalNetworkIO[T <: Data](n: Int, dType: T) extends Bundle { } class BasicCrossbarIO[T <: Data](n: Int, dType: T) extends Bundle { - val in = Vec.fill(n){Decoupled(new PhysicalNetworkIO(n,dType))}.flip - val out = Vec.fill(n){Decoupled(new PhysicalNetworkIO(n,dType))} + val in = Vec(Decoupled(new PhysicalNetworkIO(n,dType)), n).flip + val out = Vec(Decoupled(new PhysicalNetworkIO(n,dType)), n) } abstract class PhysicalNetwork extends Module @@ -27,7 +27,7 @@ abstract class PhysicalNetwork extends Module class BasicCrossbar[T <: Data](n: Int, dType: T, count: Int = 1, needsLock: Option[PhysicalNetworkIO[T] => Bool] = None) extends PhysicalNetwork { val io = new BasicCrossbarIO(n, dType) - val rdyVecs = List.fill(n){Vec.fill(n)(Wire(Bool()))} + val rdyVecs = Seq.fill(n){Seq.fill(n)(Wire(Bool()))} io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => { val rrarb = Module(new LockingRRArbiter(io.in(0).bits, n, count, needsLock)) diff --git a/uncore/src/main/scala/tilelink.scala b/uncore/src/main/scala/tilelink.scala index d281744a..6c4cf264 100644 --- a/uncore/src/main/scala/tilelink.scala +++ b/uncore/src/main/scala/tilelink.scala @@ -1086,7 +1086,7 @@ trait TileLinkArbiterLike extends TileLinkParameters { /** Abstract base case for any Arbiters that have UncachedTileLinkIOs */ abstract class UncachedTileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike { val io = new Bundle { - val in = Vec.fill(arbN){new UncachedTileLinkIO}.flip + val in = Vec(new UncachedTileLinkIO, arbN).flip val out = new UncachedTileLinkIO } hookupClientSource(io.in.map(_.acquire), io.out.acquire) @@ -1097,7 +1097,7 @@ abstract class UncachedTileLinkIOArbiter(val arbN: Int) extends Module with Tile /** Abstract base case for any Arbiters that have cached TileLinkIOs */ abstract class TileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike { val io = new Bundle { - val in = Vec.fill(arbN){new TileLinkIO}.flip + val in = Vec(new TileLinkIO, arbN).flip val out = new TileLinkIO } hookupClientSource(io.in.map(_.acquire), io.out.acquire) @@ -1141,7 +1141,7 @@ class TileLinkIOArbiterThatUsesNewId(val n: Int) extends TileLinkIOArbiter(n) wi /** Concrete uncached client-side arbiter that appends the arbiter's port id to client_xact_id */ class ClientUncachedTileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike with AppendsArbiterId { val io = new Bundle { - val in = Vec.fill(arbN){new ClientUncachedTileLinkIO}.flip + val in = Vec(new ClientUncachedTileLinkIO, arbN).flip val out = new ClientUncachedTileLinkIO } hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire) @@ -1151,7 +1151,7 @@ class ClientUncachedTileLinkIOArbiter(val arbN: Int) extends Module with TileLin /** Concrete client-side arbiter that appends the arbiter's port id to client_xact_id */ class ClientTileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike with AppendsArbiterId { val io = new Bundle { - val in = Vec.fill(arbN){new ClientTileLinkIO}.flip + val in = Vec(new ClientTileLinkIO, arbN).flip val out = new ClientTileLinkIO } hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire) @@ -1461,7 +1461,7 @@ class MemIOTileLinkIOConverter(qDepth: Int) extends TLModule with MIFParameters val (mif_cnt_out, mif_wrap_out) = Counter(mem_data_q.io.enq.fire(), mifDataBeats) val mif_done_out = Reg(init=Bool(false)) val tl_buf_out = Reg(Vec(io.tl.acquire.bits.data, tlDataBeats)) - val mif_buf_out = Vec.fill(mifDataBeats){ new MemData } + val mif_buf_out = Vec(new MemData, mifDataBeats) mif_buf_out := mif_buf_out.fromBits(tl_buf_out.toBits) val mif_prog_out = (mif_cnt_out+UInt(1, width = log2Up(mifDataBeats+1)))*UInt(mifDataBits) val tl_prog_out = tl_cnt_out*UInt(tlDataBits) @@ -1611,7 +1611,7 @@ class MemIOTileLinkIOConverter(qDepth: Int) extends TLModule with MIFParameters val (mif_cnt_in, mif_wrap_in) = Counter(io.mem.resp.fire(), mifDataBeats) // TODO: Assumes all resps have data val mif_done_in = Reg(init=Bool(false)) val mif_buf_in = Reg(Vec(new MemData, mifDataBeats)) - val tl_buf_in = Vec.fill(tlDataBeats){ io.tl.acquire.bits.data } + val tl_buf_in = Vec(io.tl.acquire.bits.data, tlDataBeats) tl_buf_in := tl_buf_in.fromBits(mif_buf_in.toBits) val tl_prog_in = (tl_cnt_in+UInt(1, width = log2Up(tlDataBeats+1)))*UInt(tlDataBits) val mif_prog_in = mif_cnt_in*UInt(mifDataBits) diff --git a/uncore/src/main/scala/uncore.scala b/uncore/src/main/scala/uncore.scala index fccf720f..a9cc66d6 100644 --- a/uncore/src/main/scala/uncore.scala +++ b/uncore/src/main/scala/uncore.scala @@ -50,7 +50,7 @@ trait HasCoherenceAgentWiringHelpers { trait HasInnerTLIO extends CoherenceAgentBundle { val inner = Bundle(new ManagerTileLinkIO)(innerTLParams) - val incoherent = Vec.fill(inner.tlNCachingClients){Bool()}.asInput + val incoherent = Vec(Bool(), inner.tlNCachingClients).asInput def iacq(dummy: Int = 0) = inner.acquire.bits def iprb(dummy: Int = 0) = inner.probe.bits def irel(dummy: Int = 0) = inner.release.bits diff --git a/uncore/src/main/scala/util.scala b/uncore/src/main/scala/util.scala index 4c0b27c0..8fb21f2e 100644 --- a/uncore/src/main/scala/util.scala +++ b/uncore/src/main/scala/util.scala @@ -62,7 +62,7 @@ class FlowThroughSerializer[T <: HasTileLinkData](gen: T, n: Int) extends Module val rbits = Reg{io.in.bits} val active = Reg(init=Bool(false)) - val shifter = Vec.fill(n){Bits(width = narrowWidth)} + val shifter = Vec(Bits(width = narrowWidth), n) (0 until n).foreach { i => shifter(i) := rbits.data((i+1)*narrowWidth-1,i*narrowWidth) }