riscv/rocket-chip
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Debug: Fix off-by-1 for detecting nonexistent harts.

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Megan Wachs 2017-04-07 15:22:16 -07:00 committed by Andrew Waterman
parent 01372e1686
commit 051acee76c
1 changed files with 1 additions and 1 deletions
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src/main/scala/uncore/devices/debug/Debug.scala
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@ -524,7 +524,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
val unavailVec = Wire(init = Vec.fill(nComponents){false.B})
unavailVec := io.debugUnavail
when (selectedHartReg > nComponents.U) {
when (selectedHartReg >= nComponents.U) {
DMSTATUSRdData.allnonexistent := true.B
DMSTATUSRdData.anynonexistent := true.B
}.elsewhen (unavailVec(selectedHartReg)) {