diff --git a/src/main/scala/uncore/devices/debug/Debug.scala b/src/main/scala/uncore/devices/debug/Debug.scala
index b7f04b5b..f3c2431a 100644
--- a/src/main/scala/uncore/devices/debug/Debug.scala
+++ b/src/main/scala/uncore/devices/debug/Debug.scala
@@ -524,7 +524,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
     val unavailVec = Wire(init = Vec.fill(nComponents){false.B})
     unavailVec := io.debugUnavail
 
-    when (selectedHartReg > nComponents.U) {
+    when (selectedHartReg >= nComponents.U) {
       DMSTATUSRdData.allnonexistent := true.B
       DMSTATUSRdData.anynonexistent := true.B
     }.elsewhen (unavailVec(selectedHartReg)) {