riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Avoid conflicting assigments to registers in timers. Give priority to start over stop.

Browse Source
This commit is contained in:
Matthew Naylor 2016-03-10 12:50:03 +00:00 committed by Howard Mao
parent 137b77d780
commit 04be438847
1 changed files with 5 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
groundtest/src/main/scala/util.scala
View File

@ -22,12 +22,10 @@ class Timer(initCount: Int) extends Module {
countdown := UInt(initCount - 1) countdown := UInt(initCount - 1)
active := Bool(true) active := Bool(true)
} }
.elsewhen (io.stop) {
when (io.stop) {
active := Bool(false) active := Bool(false)
} }
.elsewhen (active) {
when (active) {
countdown := countdown - UInt(1) countdown := countdown - UInt(1)
} }
@ -64,14 +62,13 @@ class DynamicTimer(width: Int) extends Module {
countdown := io.period countdown := io.period
active := Bool(true) active := Bool(true)
} }
.elsewhen (io.stop) {
active := Bool(false)
}
.elsewhen (active) { .elsewhen (active) {
countdown := countdown - UInt(1) countdown := countdown - UInt(1)
} }
when (io.stop) {
active := Bool(false)
}
io.timeout := countdown === UInt(0) && active io.timeout := countdown === UInt(0) && active
} }