From 04be438847611639bd780064dc36d81ff6db779f Mon Sep 17 00:00:00 2001
From: Matthew Naylor <mattfn@gmail.com>
Date: Thu, 10 Mar 2016 12:50:03 +0000
Subject: [PATCH] Avoid conflicting assigments to registers in timers.  Give
 priority to start over stop.

---
 groundtest/src/main/scala/util.scala | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/groundtest/src/main/scala/util.scala b/groundtest/src/main/scala/util.scala
index 3e8d5102..9ce29de5 100644
--- a/groundtest/src/main/scala/util.scala
+++ b/groundtest/src/main/scala/util.scala
@@ -22,12 +22,10 @@ class Timer(initCount: Int) extends Module {
     countdown := UInt(initCount - 1)
     active := Bool(true)
   }
-
-  when (io.stop) {
+  .elsewhen (io.stop) {
     active := Bool(false)
   }
-
-  when (active) {
+  .elsewhen (active) {
     countdown := countdown - UInt(1)
   }
 
@@ -64,14 +62,13 @@ class DynamicTimer(width: Int) extends Module {
     countdown := io.period
     active := Bool(true)
   }
+  .elsewhen (io.stop) {
+    active := Bool(false)
+  }
   .elsewhen (active) {
     countdown := countdown - UInt(1)
   }
 
-  when (io.stop) {
-    active := Bool(false)
-  }
-
   io.timeout := countdown === UInt(0) && active
 }