riscv/rocket-chip
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Chisel3 compatibility: use BitPat for don't-cares

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This one's hella ugly, but for the time being, idgaf.
This commit is contained in:
Andrew Waterman
2015-07-28 02:48:49 -07:00
parent f2dcc40e67
commit 049fc8dc24
9 changed files with 253 additions and 266 deletions
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rocket/src/main/scala/rocket.scala
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@@ -139,7 +139,7 @@ class Rocket extends CoreModule
// this is overly conservative
val safe_csrs = CSRs.sscratch :: CSRs.sepc :: CSRs.mscratch :: CSRs.mepc :: CSRs.mcause :: CSRs.mbadaddr :: Nil
val legal_csrs = collection.mutable.LinkedHashSet(CSRs.all:_*)
val id_csr_flush = id_system_insn || (id_csr_en && !id_csr_ren && !DecodeLogic(id_csr_addr, safe_csrs, legal_csrs -- safe_csrs))
val id_csr_flush = id_system_insn || (id_csr_en && !id_csr_ren && !DecodeLogic(id_csr_addr, safe_csrs.map(UInt(_)), (legal_csrs -- safe_csrs).toList.map(UInt(_))))
val id_illegal_insn = !id_ctrl.legal ||
id_ctrl.fp && !csr.io.status.fs.orR ||