From 049fc8dc24b947e68072f38e78ac036a1a8648f0 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 28 Jul 2015 02:48:49 -0700 Subject: [PATCH] Chisel3 compatibility: use BitPat for don't-cares This one's hella ugly, but for the time being, idgaf. --- rocket/src/main/scala/consts.scala | 32 +- rocket/src/main/scala/csr.scala | 2 +- rocket/src/main/scala/decode.scala | 26 +- rocket/src/main/scala/dpath_alu.scala | 30 +- rocket/src/main/scala/fpu.scala | 39 ++- rocket/src/main/scala/idecode.scala | 14 +- rocket/src/main/scala/instructions.scala | 372 +++++++++++------------ rocket/src/main/scala/multiplier.scala | 2 +- rocket/src/main/scala/rocket.scala | 2 +- 9 files changed, 253 insertions(+), 266 deletions(-) diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index 1fd8bc30..fda38fc2 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -8,22 +8,22 @@ import scala.math._ trait ScalarOpConstants { val SZ_BR = 3 - val BR_X = Bits("b???", 3) - val BR_EQ = Bits(0, 3) - val BR_NE = Bits(1, 3) - val BR_J = Bits(2, 3) - val BR_N = Bits(3, 3) - val BR_LT = Bits(4, 3) - val BR_GE = Bits(5, 3) - val BR_LTU = Bits(6, 3) - val BR_GEU = Bits(7, 3) + val BR_X = BitPat("b???") + val BR_EQ = UInt(0, 3) + val BR_NE = UInt(1, 3) + val BR_J = UInt(2, 3) + val BR_N = UInt(3, 3) + val BR_LT = UInt(4, 3) + val BR_GE = UInt(5, 3) + val BR_LTU = UInt(6, 3) + val BR_GEU = UInt(7, 3) - val A1_X = Bits("b??", 2) + val A1_X = BitPat("b??") val A1_ZERO = UInt(0, 2) val A1_RS1 = UInt(1, 2) val A1_PC = UInt(2, 2) - val IMM_X = Bits("b???", 3) + val IMM_X = BitPat("b???") val IMM_S = UInt(0, 3) val IMM_SB = UInt(1, 3) val IMM_U = UInt(2, 3) @@ -31,15 +31,15 @@ trait ScalarOpConstants { val IMM_I = UInt(4, 3) val IMM_Z = UInt(5, 3) - val A2_X = Bits("b??", 2) + val A2_X = BitPat("b??") val A2_ZERO = UInt(0, 2) val A2_FOUR = UInt(1, 2) val A2_RS2 = UInt(2, 2) val A2_IMM = UInt(3, 2) - val X = Bool.DC - val N = Bool(false) - val Y = Bool(true) + val X = BitPat("b?") + val N = BitPat("b0") + val Y = BitPat("b1") val SZ_DW = 1 val DW_X = X @@ -52,6 +52,4 @@ trait ScalarOpConstants { val PRV_S = 1 val PRV_H = 2 val PRV_M = 3 - - val RA = UInt(1, 5) } diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala index a81ee0e8..8fb09605 100644 --- a/rocket/src/main/scala/csr.scala +++ b/rocket/src/main/scala/csr.scala @@ -57,7 +57,7 @@ object CSR { // commands val SZ = 3 - val X = UInt.DC(SZ) + val X = BitPat.DC(SZ) val N = UInt(0,SZ) val W = UInt(1,SZ) val S = UInt(2,SZ) diff --git a/rocket/src/main/scala/decode.scala b/rocket/src/main/scala/decode.scala index 421ef66d..db65f8ff 100644 --- a/rocket/src/main/scala/decode.scala +++ b/rocket/src/main/scala/decode.scala @@ -6,21 +6,14 @@ import Chisel._ object DecodeLogic { - def term(b: Bits) = { - val lit = b.litOf - if (lit.isZ) { - var (bits, mask, swidth) = Literal.parseLit(lit.toString) - new Term(BigInt(bits, 2), BigInt(2).pow(lit.getWidth)-(BigInt(mask, 2)+1)) - } else { - new Term(lit.value) - } - } + def term(lit: BitPat) = + new Term(lit.value, BigInt(2).pow(lit.getWidth)-(lit.mask+1)) def logic(addr: UInt, addrWidth: Int, cache: scala.collection.mutable.Map[Term,Bool], terms: Seq[Term]) = { terms.map { t => cache.getOrElseUpdate(t, (if (t.mask == 0) addr else addr & Bits(BigInt(2).pow(addrWidth)-(t.mask+1), addrWidth)) === Bits(t.value, addrWidth)) }.foldLeft(Bool(false))(_||_) } - def apply[T <: Bits](addr: UInt, default: T, mapping: Iterable[(UInt, T)]): T = { + def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = { val cache = caches.getOrElseUpdate(addr, collection.mutable.Map[Term,Bool]()) val dterm = term(default) val (keys, values) = mapping.unzip @@ -32,7 +25,7 @@ object DecodeLogic for (u <- t.tail) assert(!t.head._2.intersects(u._2), "DecodeLogic: keys " + t.head + " and " + u + " overlap") - val result = (0 until default.litOf.getWidth.max(values.map(_.litOf.getWidth).max)).map({ case (i: Int) => + (0 until default.getWidth.max(values.map(_.getWidth).max)).map({ case (i: Int) => val mint = termvalues.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 1 }.map(_._1) val maxt = termvalues.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 0 }.map(_._1) val dc = termvalues.filter { case (k,t) => ((t.mask >> i) & 1) == 1 }.map(_._1) @@ -46,20 +39,19 @@ object DecodeLogic if (defbit == 0) bit else ~bit } }).reverse.reduceRight(Cat(_,_)) - default.fromBits(result) } - def apply[T <: Bits](addr: UInt, default: Iterable[T], mappingIn: Iterable[(UInt, Iterable[T])]): Iterable[T] = { - val mapping = collection.mutable.ArrayBuffer.fill(default.size)(collection.mutable.ArrayBuffer[(UInt, T)]()) + def apply(addr: UInt, default: Iterable[BitPat], mappingIn: Iterable[(BitPat, Iterable[BitPat])]): Iterable[UInt] = { + val mapping = collection.mutable.ArrayBuffer.fill(default.size)(collection.mutable.ArrayBuffer[(BitPat, BitPat)]()) for ((key, values) <- mappingIn) for ((value, i) <- values zipWithIndex) mapping(i) += key -> value for ((thisDefault, thisMapping) <- default zip mapping) yield apply(addr, thisDefault, thisMapping) } + def apply(addr: UInt, default: Iterable[BitPat], mappingIn: List[(UInt, Iterable[BitPat])]): Iterable[UInt] = + apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Iterable[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = - apply(addr, Bool.DC, trues.map(_ -> Bool(true)) ++ falses.map(_ -> Bool(false))) - def apply(addr: UInt, tru: UInt, fals: UInt): Bool = - apply(addr, Seq(tru), Seq(fals)) + apply(addr, BitPat.DC(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).toBool private val caches = collection.mutable.Map[UInt,collection.mutable.Map[Term,Bool]]() } diff --git a/rocket/src/main/scala/dpath_alu.scala b/rocket/src/main/scala/dpath_alu.scala index 16de87eb..354934ca 100644 --- a/rocket/src/main/scala/dpath_alu.scala +++ b/rocket/src/main/scala/dpath_alu.scala @@ -8,21 +8,21 @@ import Instructions._ object ALU { val SZ_ALU_FN = 4 - val FN_X = Bits("b????") - val FN_ADD = Bits(0) - val FN_SL = Bits(1) - val FN_XOR = Bits(4) - val FN_OR = Bits(6) - val FN_AND = Bits(7) - val FN_SR = Bits(5) - val FN_SEQ = Bits(8) - val FN_SNE = Bits(9) - val FN_SUB = Bits(10) - val FN_SRA = Bits(11) - val FN_SLT = Bits(12) - val FN_SGE = Bits(13) - val FN_SLTU = Bits(14) - val FN_SGEU = Bits(15) + val FN_X = BitPat("b????") + val FN_ADD = UInt(0) + val FN_SL = UInt(1) + val FN_XOR = UInt(4) + val FN_OR = UInt(6) + val FN_AND = UInt(7) + val FN_SR = UInt(5) + val FN_SEQ = UInt(8) + val FN_SNE = UInt(9) + val FN_SUB = UInt(10) + val FN_SRA = UInt(11) + val FN_SLT = UInt(12) + val FN_SGE = UInt(13) + val FN_SLTU = UInt(14) + val FN_SGEU = UInt(15) val FN_DIV = FN_XOR val FN_DIVU = FN_SR diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index a6b32b49..c1c9e1e5 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -13,24 +13,24 @@ case object DFMALatency object FPConstants { - val FCMD_ADD = Bits("b0??00") - val FCMD_SUB = Bits("b0??01") - val FCMD_MUL = Bits("b0??10") - val FCMD_MADD = Bits("b1??00") - val FCMD_MSUB = Bits("b1??01") - val FCMD_NMSUB = Bits("b1??10") - val FCMD_NMADD = Bits("b1??11") - val FCMD_DIV = Bits("b?0011") - val FCMD_SQRT = Bits("b?1011") - val FCMD_SGNJ = Bits("b??1?0") - val FCMD_MINMAX = Bits("b?01?1") - val FCMD_CVT_FF = Bits("b??0??") - val FCMD_CVT_IF = Bits("b?10??") - val FCMD_CMP = Bits("b?01??") - val FCMD_MV_XF = Bits("b?11??") - val FCMD_CVT_FI = Bits("b??0??") - val FCMD_MV_FX = Bits("b??1??") - val FCMD_X = Bits("b?????") + val FCMD_ADD = BitPat("b0??00") + val FCMD_SUB = BitPat("b0??01") + val FCMD_MUL = BitPat("b0??10") + val FCMD_MADD = BitPat("b1??00") + val FCMD_MSUB = BitPat("b1??01") + val FCMD_NMSUB = BitPat("b1??10") + val FCMD_NMADD = BitPat("b1??11") + val FCMD_DIV = BitPat("b?0011") + val FCMD_SQRT = BitPat("b?1011") + val FCMD_SGNJ = BitPat("b??1?0") + val FCMD_MINMAX = BitPat("b?01?1") + val FCMD_CVT_FF = BitPat("b??0??") + val FCMD_CVT_IF = BitPat("b?10??") + val FCMD_CMP = BitPat("b?01??") + val FCMD_MV_XF = BitPat("b?11??") + val FCMD_CVT_FI = BitPat("b??0??") + val FCMD_MV_FX = BitPat("b??1??") + val FCMD_X = BitPat("b?????") val FCMD_WIDTH = 5 val RM_SZ = 3 @@ -65,9 +65,6 @@ class FPUDecoder extends Module val sigs = new FPUCtrlSigs().asOutput } - val N = Bool(false) - val Y = Bool(true) - val X = Bool(false) val decoder = DecodeLogic(io.inst, List (FCMD_X, X,X,X,X,X,X,X,X,X,X,X,X,X,X,X,X), Array(FLW -> List(FCMD_X, Y,Y,N,N,N,X,X,Y,N,N,N,N,N,N,N,N), diff --git a/rocket/src/main/scala/idecode.scala b/rocket/src/main/scala/idecode.scala index 18a24616..97058bd4 100644 --- a/rocket/src/main/scala/idecode.scala +++ b/rocket/src/main/scala/idecode.scala @@ -11,7 +11,7 @@ abstract trait DecodeConstants { val xpr64 = Y - val decode_default = + val decode_default: List[BitPat] = // jal renf1 fence.i // | jalr | renf2 | // fp_val| | renx2 | | renf3 | @@ -22,7 +22,7 @@ abstract trait DecodeConstants // | | | | | | | | | | | | | | | | | | | | | | | | | | List(N, X,X,X,X,X,X,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, X,X,X,X,X,X,CSR.X,X,X,X) - val table: Array[(UInt, List[UInt])] + val table: Array[(BitPat, List[BitPat])] } class IntCtrlSigs extends Bundle { @@ -53,7 +53,7 @@ class IntCtrlSigs extends Bundle { val fence = Bool() val amo = Bool() - def decode(inst: UInt, table: Iterable[(UInt, List[UInt])]) = { + def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = { val decoder = DecodeLogic(inst, XDecode.decode_default, table) Vec(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, sel_alu2, sel_alu1, sel_imm, alu_dw, alu_fn, mem, mem_cmd, mem_type, @@ -64,7 +64,7 @@ class IntCtrlSigs extends Bundle { object XDecode extends DecodeConstants { - val table = Array( + val table: Array[(BitPat, List[BitPat])] = Array( // jal renf1 fence.i // | jalr | renf2 | // fp_val| | renx2 | | renf3 | @@ -185,7 +185,7 @@ object XDecode extends DecodeConstants object FDecode extends DecodeConstants { - val table = Array( + val table: Array[(BitPat, List[BitPat])] = Array( // jal renf1 fence.i // | jalr | renf2 | // fp_val| | renx2 | | renf3 | @@ -256,7 +256,7 @@ object FDecode extends DecodeConstants object FDivSqrtDecode extends DecodeConstants { - val table = Array( + val table: Array[(BitPat, List[BitPat])] = Array( FDIV_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N), FDIV_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N), FSQRT_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N), @@ -265,7 +265,7 @@ object FDivSqrtDecode extends DecodeConstants object RoCCDecode extends DecodeConstants { - val table = Array( + val table: Array[(BitPat, List[BitPat])] = Array( // jal renf1 fence.i // | jalr | renf2 | // fp_val| | renx2 | | renf3 | diff --git a/rocket/src/main/scala/instructions.scala b/rocket/src/main/scala/instructions.scala index 170e7416..f007ebc4 100644 --- a/rocket/src/main/scala/instructions.scala +++ b/rocket/src/main/scala/instructions.scala @@ -6,192 +6,192 @@ import Chisel._ /* Automatically generated by parse-opcodes */ object Instructions { - def BEQ = Bits("b?????????????????000?????1100011") - def BNE = Bits("b?????????????????001?????1100011") - def BLT = Bits("b?????????????????100?????1100011") - def BGE = Bits("b?????????????????101?????1100011") - def BLTU = Bits("b?????????????????110?????1100011") - def BGEU = Bits("b?????????????????111?????1100011") - def JALR = Bits("b?????????????????000?????1100111") - def JAL = Bits("b?????????????????????????1101111") - def LUI = Bits("b?????????????????????????0110111") - def AUIPC = Bits("b?????????????????????????0010111") - def ADDI = Bits("b?????????????????000?????0010011") - def SLLI = Bits("b000000???????????001?????0010011") - def SLTI = Bits("b?????????????????010?????0010011") - def SLTIU = Bits("b?????????????????011?????0010011") - def XORI = Bits("b?????????????????100?????0010011") - def SRLI = Bits("b000000???????????101?????0010011") - def SRAI = Bits("b010000???????????101?????0010011") - def ORI = Bits("b?????????????????110?????0010011") - def ANDI = Bits("b?????????????????111?????0010011") - def ADD = Bits("b0000000??????????000?????0110011") - def SUB = Bits("b0100000??????????000?????0110011") - def SLL = Bits("b0000000??????????001?????0110011") - def SLT = Bits("b0000000??????????010?????0110011") - def SLTU = Bits("b0000000??????????011?????0110011") - def XOR = Bits("b0000000??????????100?????0110011") - def SRL = Bits("b0000000??????????101?????0110011") - def SRA = Bits("b0100000??????????101?????0110011") - def OR = Bits("b0000000??????????110?????0110011") - def AND = Bits("b0000000??????????111?????0110011") - def ADDIW = Bits("b?????????????????000?????0011011") - def SLLIW = Bits("b0000000??????????001?????0011011") - def SRLIW = Bits("b0000000??????????101?????0011011") - def SRAIW = Bits("b0100000??????????101?????0011011") - def ADDW = Bits("b0000000??????????000?????0111011") - def SUBW = Bits("b0100000??????????000?????0111011") - def SLLW = Bits("b0000000??????????001?????0111011") - def SRLW = Bits("b0000000??????????101?????0111011") - def SRAW = Bits("b0100000??????????101?????0111011") - def LB = Bits("b?????????????????000?????0000011") - def LH = Bits("b?????????????????001?????0000011") - def LW = Bits("b?????????????????010?????0000011") - def LD = Bits("b?????????????????011?????0000011") - def LBU = Bits("b?????????????????100?????0000011") - def LHU = Bits("b?????????????????101?????0000011") - def LWU = Bits("b?????????????????110?????0000011") - def SB = Bits("b?????????????????000?????0100011") - def SH = Bits("b?????????????????001?????0100011") - def SW = Bits("b?????????????????010?????0100011") - def SD = Bits("b?????????????????011?????0100011") - def FENCE = Bits("b?????????????????000?????0001111") - def FENCE_I = Bits("b?????????????????001?????0001111") - def MUL = Bits("b0000001??????????000?????0110011") - def MULH = Bits("b0000001??????????001?????0110011") - def MULHSU = Bits("b0000001??????????010?????0110011") - def MULHU = Bits("b0000001??????????011?????0110011") - def DIV = Bits("b0000001??????????100?????0110011") - def DIVU = Bits("b0000001??????????101?????0110011") - def REM = Bits("b0000001??????????110?????0110011") - def REMU = Bits("b0000001??????????111?????0110011") - def MULW = Bits("b0000001??????????000?????0111011") - def DIVW = Bits("b0000001??????????100?????0111011") - def DIVUW = Bits("b0000001??????????101?????0111011") - def REMW = Bits("b0000001??????????110?????0111011") - def REMUW = Bits("b0000001??????????111?????0111011") - def AMOADD_W = Bits("b00000????????????010?????0101111") - def AMOXOR_W = Bits("b00100????????????010?????0101111") - def AMOOR_W = Bits("b01000????????????010?????0101111") - def AMOAND_W = Bits("b01100????????????010?????0101111") - def AMOMIN_W = Bits("b10000????????????010?????0101111") - def AMOMAX_W = Bits("b10100????????????010?????0101111") - def AMOMINU_W = Bits("b11000????????????010?????0101111") - def AMOMAXU_W = Bits("b11100????????????010?????0101111") - def AMOSWAP_W = Bits("b00001????????????010?????0101111") - def LR_W = Bits("b00010??00000?????010?????0101111") - def SC_W = Bits("b00011????????????010?????0101111") - def AMOADD_D = Bits("b00000????????????011?????0101111") - def AMOXOR_D = Bits("b00100????????????011?????0101111") - def AMOOR_D = Bits("b01000????????????011?????0101111") - def AMOAND_D = Bits("b01100????????????011?????0101111") - def AMOMIN_D = Bits("b10000????????????011?????0101111") - def AMOMAX_D = Bits("b10100????????????011?????0101111") - def AMOMINU_D = Bits("b11000????????????011?????0101111") - def AMOMAXU_D = Bits("b11100????????????011?????0101111") - def AMOSWAP_D = Bits("b00001????????????011?????0101111") - def LR_D = Bits("b00010??00000?????011?????0101111") - def SC_D = Bits("b00011????????????011?????0101111") - def SCALL = Bits("b00000000000000000000000001110011") - def SBREAK = Bits("b00000000000100000000000001110011") - def SRET = Bits("b00010000000000000000000001110011") - def SFENCE_VM = Bits("b000100000001?????000000001110011") - def WFI = Bits("b00010000001000000000000001110011") - def MRTH = Bits("b00110000011000000000000001110011") - def MRTS = Bits("b00110000010100000000000001110011") - def HRTS = Bits("b00100000010100000000000001110011") - def CSRRW = Bits("b?????????????????001?????1110011") - def CSRRS = Bits("b?????????????????010?????1110011") - def CSRRC = Bits("b?????????????????011?????1110011") - def CSRRWI = Bits("b?????????????????101?????1110011") - def CSRRSI = Bits("b?????????????????110?????1110011") - def CSRRCI = Bits("b?????????????????111?????1110011") - def FADD_S = Bits("b0000000??????????????????1010011") - def FSUB_S = Bits("b0000100??????????????????1010011") - def FMUL_S = Bits("b0001000??????????????????1010011") - def FDIV_S = Bits("b0001100??????????????????1010011") - def FSGNJ_S = Bits("b0010000??????????000?????1010011") - def FSGNJN_S = Bits("b0010000??????????001?????1010011") - def FSGNJX_S = Bits("b0010000??????????010?????1010011") - def FMIN_S = Bits("b0010100??????????000?????1010011") - def FMAX_S = Bits("b0010100??????????001?????1010011") - def FSQRT_S = Bits("b010110000000?????????????1010011") - def FADD_D = Bits("b0000001??????????????????1010011") - def FSUB_D = Bits("b0000101??????????????????1010011") - def FMUL_D = Bits("b0001001??????????????????1010011") - def FDIV_D = Bits("b0001101??????????????????1010011") - def FSGNJ_D = Bits("b0010001??????????000?????1010011") - def FSGNJN_D = Bits("b0010001??????????001?????1010011") - def FSGNJX_D = Bits("b0010001??????????010?????1010011") - def FMIN_D = Bits("b0010101??????????000?????1010011") - def FMAX_D = Bits("b0010101??????????001?????1010011") - def FCVT_S_D = Bits("b010000000001?????????????1010011") - def FCVT_D_S = Bits("b010000100000?????????????1010011") - def FSQRT_D = Bits("b010110100000?????????????1010011") - def FLE_S = Bits("b1010000??????????000?????1010011") - def FLT_S = Bits("b1010000??????????001?????1010011") - def FEQ_S = Bits("b1010000??????????010?????1010011") - def FLE_D = Bits("b1010001??????????000?????1010011") - def FLT_D = Bits("b1010001??????????001?????1010011") - def FEQ_D = Bits("b1010001??????????010?????1010011") - def FCVT_W_S = Bits("b110000000000?????????????1010011") - def FCVT_WU_S = Bits("b110000000001?????????????1010011") - def FCVT_L_S = Bits("b110000000010?????????????1010011") - def FCVT_LU_S = Bits("b110000000011?????????????1010011") - def FMV_X_S = Bits("b111000000000?????000?????1010011") - def FCLASS_S = Bits("b111000000000?????001?????1010011") - def FCVT_W_D = Bits("b110000100000?????????????1010011") - def FCVT_WU_D = Bits("b110000100001?????????????1010011") - def FCVT_L_D = Bits("b110000100010?????????????1010011") - def FCVT_LU_D = Bits("b110000100011?????????????1010011") - def FMV_X_D = Bits("b111000100000?????000?????1010011") - def FCLASS_D = Bits("b111000100000?????001?????1010011") - def FCVT_S_W = Bits("b110100000000?????????????1010011") - def FCVT_S_WU = Bits("b110100000001?????????????1010011") - def FCVT_S_L = Bits("b110100000010?????????????1010011") - def FCVT_S_LU = Bits("b110100000011?????????????1010011") - def FMV_S_X = Bits("b111100000000?????000?????1010011") - def FCVT_D_W = Bits("b110100100000?????????????1010011") - def FCVT_D_WU = Bits("b110100100001?????????????1010011") - def FCVT_D_L = Bits("b110100100010?????????????1010011") - def FCVT_D_LU = Bits("b110100100011?????????????1010011") - def FMV_D_X = Bits("b111100100000?????000?????1010011") - def FLW = Bits("b?????????????????010?????0000111") - def FLD = Bits("b?????????????????011?????0000111") - def FSW = Bits("b?????????????????010?????0100111") - def FSD = Bits("b?????????????????011?????0100111") - def FMADD_S = Bits("b?????00??????????????????1000011") - def FMSUB_S = Bits("b?????00??????????????????1000111") - def FNMSUB_S = Bits("b?????00??????????????????1001011") - def FNMADD_S = Bits("b?????00??????????????????1001111") - def FMADD_D = Bits("b?????01??????????????????1000011") - def FMSUB_D = Bits("b?????01??????????????????1000111") - def FNMSUB_D = Bits("b?????01??????????????????1001011") - def FNMADD_D = Bits("b?????01??????????????????1001111") - def CUSTOM0 = Bits("b?????????????????000?????0001011") - def CUSTOM0_RS1 = Bits("b?????????????????010?????0001011") - def CUSTOM0_RS1_RS2 = Bits("b?????????????????011?????0001011") - def CUSTOM0_RD = Bits("b?????????????????100?????0001011") - def CUSTOM0_RD_RS1 = Bits("b?????????????????110?????0001011") - def CUSTOM0_RD_RS1_RS2 = Bits("b?????????????????111?????0001011") - def CUSTOM1 = Bits("b?????????????????000?????0101011") - def CUSTOM1_RS1 = Bits("b?????????????????010?????0101011") - def CUSTOM1_RS1_RS2 = Bits("b?????????????????011?????0101011") - def CUSTOM1_RD = Bits("b?????????????????100?????0101011") - def CUSTOM1_RD_RS1 = Bits("b?????????????????110?????0101011") - def CUSTOM1_RD_RS1_RS2 = Bits("b?????????????????111?????0101011") - def CUSTOM2 = Bits("b?????????????????000?????1011011") - def CUSTOM2_RS1 = Bits("b?????????????????010?????1011011") - def CUSTOM2_RS1_RS2 = Bits("b?????????????????011?????1011011") - def CUSTOM2_RD = Bits("b?????????????????100?????1011011") - def CUSTOM2_RD_RS1 = Bits("b?????????????????110?????1011011") - def CUSTOM2_RD_RS1_RS2 = Bits("b?????????????????111?????1011011") - def CUSTOM3 = Bits("b?????????????????000?????1111011") - def CUSTOM3_RS1 = Bits("b?????????????????010?????1111011") - def CUSTOM3_RS1_RS2 = Bits("b?????????????????011?????1111011") - def CUSTOM3_RD = Bits("b?????????????????100?????1111011") - def CUSTOM3_RD_RS1 = Bits("b?????????????????110?????1111011") - def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011") + def BEQ = BitPat("b?????????????????000?????1100011") + def BNE = BitPat("b?????????????????001?????1100011") + def BLT = BitPat("b?????????????????100?????1100011") + def BGE = BitPat("b?????????????????101?????1100011") + def BLTU = BitPat("b?????????????????110?????1100011") + def BGEU = BitPat("b?????????????????111?????1100011") + def JALR = BitPat("b?????????????????000?????1100111") + def JAL = BitPat("b?????????????????????????1101111") + def LUI = BitPat("b?????????????????????????0110111") + def AUIPC = BitPat("b?????????????????????????0010111") + def ADDI = BitPat("b?????????????????000?????0010011") + def SLLI = BitPat("b000000???????????001?????0010011") + def SLTI = BitPat("b?????????????????010?????0010011") + def SLTIU = BitPat("b?????????????????011?????0010011") + def XORI = BitPat("b?????????????????100?????0010011") + def SRLI = BitPat("b000000???????????101?????0010011") + def SRAI = BitPat("b010000???????????101?????0010011") + def ORI = BitPat("b?????????????????110?????0010011") + def ANDI = BitPat("b?????????????????111?????0010011") + def ADD = BitPat("b0000000??????????000?????0110011") + def SUB = BitPat("b0100000??????????000?????0110011") + def SLL = BitPat("b0000000??????????001?????0110011") + def SLT = BitPat("b0000000??????????010?????0110011") + def SLTU = BitPat("b0000000??????????011?????0110011") + def XOR = BitPat("b0000000??????????100?????0110011") + def SRL = BitPat("b0000000??????????101?????0110011") + def SRA = BitPat("b0100000??????????101?????0110011") + def OR = BitPat("b0000000??????????110?????0110011") + def AND = BitPat("b0000000??????????111?????0110011") + def ADDIW = BitPat("b?????????????????000?????0011011") + def SLLIW = BitPat("b0000000??????????001?????0011011") + def SRLIW = BitPat("b0000000??????????101?????0011011") + def SRAIW = BitPat("b0100000??????????101?????0011011") + def ADDW = BitPat("b0000000??????????000?????0111011") + def SUBW = BitPat("b0100000??????????000?????0111011") + def SLLW = BitPat("b0000000??????????001?????0111011") + def SRLW = BitPat("b0000000??????????101?????0111011") + def SRAW = BitPat("b0100000??????????101?????0111011") + def LB = BitPat("b?????????????????000?????0000011") + def LH = BitPat("b?????????????????001?????0000011") + def LW = BitPat("b?????????????????010?????0000011") + def LD = BitPat("b?????????????????011?????0000011") + def LBU = BitPat("b?????????????????100?????0000011") + def LHU = BitPat("b?????????????????101?????0000011") + def LWU = BitPat("b?????????????????110?????0000011") + def SB = BitPat("b?????????????????000?????0100011") + def SH = BitPat("b?????????????????001?????0100011") + def SW = BitPat("b?????????????????010?????0100011") + def SD = BitPat("b?????????????????011?????0100011") + def FENCE = BitPat("b?????????????????000?????0001111") + def FENCE_I = BitPat("b?????????????????001?????0001111") + def MUL = BitPat("b0000001??????????000?????0110011") + def MULH = BitPat("b0000001??????????001?????0110011") + def MULHSU = BitPat("b0000001??????????010?????0110011") + def MULHU = BitPat("b0000001??????????011?????0110011") + def DIV = BitPat("b0000001??????????100?????0110011") + def DIVU = BitPat("b0000001??????????101?????0110011") + def REM = BitPat("b0000001??????????110?????0110011") + def REMU = BitPat("b0000001??????????111?????0110011") + def MULW = BitPat("b0000001??????????000?????0111011") + def DIVW = BitPat("b0000001??????????100?????0111011") + def DIVUW = BitPat("b0000001??????????101?????0111011") + def REMW = BitPat("b0000001??????????110?????0111011") + def REMUW = BitPat("b0000001??????????111?????0111011") + def AMOADD_W = BitPat("b00000????????????010?????0101111") + def AMOXOR_W = BitPat("b00100????????????010?????0101111") + def AMOOR_W = BitPat("b01000????????????010?????0101111") + def AMOAND_W = BitPat("b01100????????????010?????0101111") + def AMOMIN_W = BitPat("b10000????????????010?????0101111") + def AMOMAX_W = BitPat("b10100????????????010?????0101111") + def AMOMINU_W = BitPat("b11000????????????010?????0101111") + def AMOMAXU_W = BitPat("b11100????????????010?????0101111") + def AMOSWAP_W = BitPat("b00001????????????010?????0101111") + def LR_W = BitPat("b00010??00000?????010?????0101111") + def SC_W = BitPat("b00011????????????010?????0101111") + def AMOADD_D = BitPat("b00000????????????011?????0101111") + def AMOXOR_D = BitPat("b00100????????????011?????0101111") + def AMOOR_D = BitPat("b01000????????????011?????0101111") + def AMOAND_D = BitPat("b01100????????????011?????0101111") + def AMOMIN_D = BitPat("b10000????????????011?????0101111") + def AMOMAX_D = BitPat("b10100????????????011?????0101111") + def AMOMINU_D = BitPat("b11000????????????011?????0101111") + def AMOMAXU_D = BitPat("b11100????????????011?????0101111") + def AMOSWAP_D = BitPat("b00001????????????011?????0101111") + def LR_D = BitPat("b00010??00000?????011?????0101111") + def SC_D = BitPat("b00011????????????011?????0101111") + def SCALL = BitPat("b00000000000000000000000001110011") + def SBREAK = BitPat("b00000000000100000000000001110011") + def SRET = BitPat("b00010000000000000000000001110011") + def SFENCE_VM = BitPat("b000100000001?????000000001110011") + def WFI = BitPat("b00010000001000000000000001110011") + def MRTH = BitPat("b00110000011000000000000001110011") + def MRTS = BitPat("b00110000010100000000000001110011") + def HRTS = BitPat("b00100000010100000000000001110011") + def CSRRW = BitPat("b?????????????????001?????1110011") + def CSRRS = BitPat("b?????????????????010?????1110011") + def CSRRC = BitPat("b?????????????????011?????1110011") + def CSRRWI = BitPat("b?????????????????101?????1110011") + def CSRRSI = BitPat("b?????????????????110?????1110011") + def CSRRCI = BitPat("b?????????????????111?????1110011") + def FADD_S = BitPat("b0000000??????????????????1010011") + def FSUB_S = BitPat("b0000100??????????????????1010011") + def FMUL_S = BitPat("b0001000??????????????????1010011") + def FDIV_S = BitPat("b0001100??????????????????1010011") + def FSGNJ_S = BitPat("b0010000??????????000?????1010011") + def FSGNJN_S = BitPat("b0010000??????????001?????1010011") + def FSGNJX_S = BitPat("b0010000??????????010?????1010011") + def FMIN_S = BitPat("b0010100??????????000?????1010011") + def FMAX_S = BitPat("b0010100??????????001?????1010011") + def FSQRT_S = BitPat("b010110000000?????????????1010011") + def FADD_D = BitPat("b0000001??????????????????1010011") + def FSUB_D = BitPat("b0000101??????????????????1010011") + def FMUL_D = BitPat("b0001001??????????????????1010011") + def FDIV_D = BitPat("b0001101??????????????????1010011") + def FSGNJ_D = BitPat("b0010001??????????000?????1010011") + def FSGNJN_D = BitPat("b0010001??????????001?????1010011") + def FSGNJX_D = BitPat("b0010001??????????010?????1010011") + def FMIN_D = BitPat("b0010101??????????000?????1010011") + def FMAX_D = BitPat("b0010101??????????001?????1010011") + def FCVT_S_D = BitPat("b010000000001?????????????1010011") + def FCVT_D_S = BitPat("b010000100000?????????????1010011") + def FSQRT_D = BitPat("b010110100000?????????????1010011") + def FLE_S = BitPat("b1010000??????????000?????1010011") + def FLT_S = BitPat("b1010000??????????001?????1010011") + def FEQ_S = BitPat("b1010000??????????010?????1010011") + def FLE_D = BitPat("b1010001??????????000?????1010011") + def FLT_D = BitPat("b1010001??????????001?????1010011") + def FEQ_D = BitPat("b1010001??????????010?????1010011") + def FCVT_W_S = BitPat("b110000000000?????????????1010011") + def FCVT_WU_S = BitPat("b110000000001?????????????1010011") + def FCVT_L_S = BitPat("b110000000010?????????????1010011") + def FCVT_LU_S = BitPat("b110000000011?????????????1010011") + def FMV_X_S = BitPat("b111000000000?????000?????1010011") + def FCLASS_S = BitPat("b111000000000?????001?????1010011") + def FCVT_W_D = BitPat("b110000100000?????????????1010011") + def FCVT_WU_D = BitPat("b110000100001?????????????1010011") + def FCVT_L_D = BitPat("b110000100010?????????????1010011") + def FCVT_LU_D = BitPat("b110000100011?????????????1010011") + def FMV_X_D = BitPat("b111000100000?????000?????1010011") + def FCLASS_D = BitPat("b111000100000?????001?????1010011") + def FCVT_S_W = BitPat("b110100000000?????????????1010011") + def FCVT_S_WU = BitPat("b110100000001?????????????1010011") + def FCVT_S_L = BitPat("b110100000010?????????????1010011") + def FCVT_S_LU = BitPat("b110100000011?????????????1010011") + def FMV_S_X = BitPat("b111100000000?????000?????1010011") + def FCVT_D_W = BitPat("b110100100000?????????????1010011") + def FCVT_D_WU = BitPat("b110100100001?????????????1010011") + def FCVT_D_L = BitPat("b110100100010?????????????1010011") + def FCVT_D_LU = BitPat("b110100100011?????????????1010011") + def FMV_D_X = BitPat("b111100100000?????000?????1010011") + def FLW = BitPat("b?????????????????010?????0000111") + def FLD = BitPat("b?????????????????011?????0000111") + def FSW = BitPat("b?????????????????010?????0100111") + def FSD = BitPat("b?????????????????011?????0100111") + def FMADD_S = BitPat("b?????00??????????????????1000011") + def FMSUB_S = BitPat("b?????00??????????????????1000111") + def FNMSUB_S = BitPat("b?????00??????????????????1001011") + def FNMADD_S = BitPat("b?????00??????????????????1001111") + def FMADD_D = BitPat("b?????01??????????????????1000011") + def FMSUB_D = BitPat("b?????01??????????????????1000111") + def FNMSUB_D = BitPat("b?????01??????????????????1001011") + def FNMADD_D = BitPat("b?????01??????????????????1001111") + def CUSTOM0 = BitPat("b?????????????????000?????0001011") + def CUSTOM0_RS1 = BitPat("b?????????????????010?????0001011") + def CUSTOM0_RS1_RS2 = BitPat("b?????????????????011?????0001011") + def CUSTOM0_RD = BitPat("b?????????????????100?????0001011") + def CUSTOM0_RD_RS1 = BitPat("b?????????????????110?????0001011") + def CUSTOM0_RD_RS1_RS2 = BitPat("b?????????????????111?????0001011") + def CUSTOM1 = BitPat("b?????????????????000?????0101011") + def CUSTOM1_RS1 = BitPat("b?????????????????010?????0101011") + def CUSTOM1_RS1_RS2 = BitPat("b?????????????????011?????0101011") + def CUSTOM1_RD = BitPat("b?????????????????100?????0101011") + def CUSTOM1_RD_RS1 = BitPat("b?????????????????110?????0101011") + def CUSTOM1_RD_RS1_RS2 = BitPat("b?????????????????111?????0101011") + def CUSTOM2 = BitPat("b?????????????????000?????1011011") + def CUSTOM2_RS1 = BitPat("b?????????????????010?????1011011") + def CUSTOM2_RS1_RS2 = BitPat("b?????????????????011?????1011011") + def CUSTOM2_RD = BitPat("b?????????????????100?????1011011") + def CUSTOM2_RD_RS1 = BitPat("b?????????????????110?????1011011") + def CUSTOM2_RD_RS1_RS2 = BitPat("b?????????????????111?????1011011") + def CUSTOM3 = BitPat("b?????????????????000?????1111011") + def CUSTOM3_RS1 = BitPat("b?????????????????010?????1111011") + def CUSTOM3_RS1_RS2 = BitPat("b?????????????????011?????1111011") + def CUSTOM3_RD = BitPat("b?????????????????100?????1111011") + def CUSTOM3_RD_RS1 = BitPat("b?????????????????110?????1111011") + def CUSTOM3_RD_RS1_RS2 = BitPat("b?????????????????111?????1111011") } object Causes { val misaligned_fetch = 0x0 diff --git a/rocket/src/main/scala/multiplier.scala b/rocket/src/main/scala/multiplier.scala index 2b0ca819..b76851f9 100644 --- a/rocket/src/main/scala/multiplier.scala +++ b/rocket/src/main/scala/multiplier.scala @@ -50,7 +50,7 @@ class MulDiv(mulUnroll: Int = 1, earlyOut: Boolean = false) extends Module { FN_MUL -> List(Y, N, X, X), FN_MULH -> List(Y, Y, Y, Y), FN_MULHU -> List(Y, Y, N, N), - FN_MULHSU -> List(Y, Y, Y, N))) + FN_MULHSU -> List(Y, Y, Y, N))).map(_ toBool) def sext(x: Bits, signed: Bool) = { val sign = signed && Mux(io.req.bits.dw === DW_64, x(w-1), x(w/2-1)) diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala index 7fb5410d..0f65e0cf 100644 --- a/rocket/src/main/scala/rocket.scala +++ b/rocket/src/main/scala/rocket.scala @@ -139,7 +139,7 @@ class Rocket extends CoreModule // this is overly conservative val safe_csrs = CSRs.sscratch :: CSRs.sepc :: CSRs.mscratch :: CSRs.mepc :: CSRs.mcause :: CSRs.mbadaddr :: Nil val legal_csrs = collection.mutable.LinkedHashSet(CSRs.all:_*) - val id_csr_flush = id_system_insn || (id_csr_en && !id_csr_ren && !DecodeLogic(id_csr_addr, safe_csrs, legal_csrs -- safe_csrs)) + val id_csr_flush = id_system_insn || (id_csr_en && !id_csr_ren && !DecodeLogic(id_csr_addr, safe_csrs.map(UInt(_)), (legal_csrs -- safe_csrs).toList.map(UInt(_)))) val id_illegal_insn = !id_ctrl.legal || id_ctrl.fp && !csr.io.status.fs.orR ||