moving util out into Chisel standard library
This commit is contained in:
Huy Vo
@ -4,23 +4,6 @@ import Chisel._
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import Node._
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import scala.math._
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object foldR
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{
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def apply[T <: Bits](x: Seq[T])(f: (T, T) => T): T =
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if (x.length == 1) x(0) else f(x(0), foldR(x.slice(1, x.length))(f))
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}
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object log2up
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{
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def apply(in: Int) = ceil(log(in)/log(2)).toInt
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}
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object ispow2
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{
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def apply(in: Int) = in > 0 && ((in & (in-1)) == 0)
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}
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object FillInterleaved
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{
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def apply(n: Int, in: Bits) =
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@ -32,109 +15,6 @@ object FillInterleaved
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}
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}
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// http://aggregate.ee.engr.uky.edu/MAGIC/#Population%20Count%20%28Ones%20Count%29
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// http://bits.stephan-brumme.com/countBits.html
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object PopCount
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{
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def apply(in: Bits) =
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{
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require(in.width <= 32)
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val w = log2up(in.width+1)
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var x = in
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if(in.width == 2) {
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x = x - ((x >> UFix(1)) & Bits("h_5555_5555"))
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} else if(in.width <= 4) {
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x = x - ((x >> UFix(1)) & Bits("h_5555_5555"))
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x = (((x >> UFix(2)) & Bits("h_3333_3333")) + (x & Bits("h_3333_3333")))
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} else if(in.width <= 8) {
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x = x - ((x >> UFix(1)) & Bits("h_5555_5555"))
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x = (((x >> UFix(2)) & Bits("h_3333_3333")) + (x & Bits("h_3333_3333")))
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x = ((x >> UFix(4)) + x)
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} else {
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// count bits of each 2-bit chunk
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x = x - ((x >> UFix(1)) & Bits("h_5555_5555"))
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// count bits of each 4-bit chunk
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x = (((x >> UFix(2)) & Bits("h_3333_3333")) + (x & Bits("h_3333_3333")))
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// count bits of each 8-bit chunk
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x = ((x >> UFix(4)) + x)
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// mask junk in upper bits
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x = x & Bits("h_0f0f_0f0f")
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// add all four 8-bit chunks
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x = x + (x >> UFix(8))
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x = x + (x >> UFix(16))
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}
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x(w-1,0)
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}
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}
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object Reverse
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{
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def doit(in: Bits, base: Int, length: Int): Bits =
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{
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val half = (1 << log2up(length))/2
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if (length == 1)
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in(base)
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else
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Cat(doit(in, base, half), doit(in, base+half, length-half))
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}
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def apply(in: Bits) = doit(in, 0, in.getWidth)
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}
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object OHToUFix
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{
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def apply(in: Seq[Bits]): UFix = {
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if (in.size <= 1) return UFix(0)
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if (in.size == 2) return in(1)
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val hi = in.slice(in.size/2, in.size)
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val lo = in.slice(0, in.size/2)
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Cat(hi.reduceLeft(_||_), apply(hi zip lo map { case (x, y) => x || y }))
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}
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def apply(in: Bits): UFix = apply((0 until in.getWidth).map(in(_)))
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}
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object UFixToOH
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{
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def apply(in: UFix, width: Int): Bits =
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{
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(UFix(1) << in(log2up(width)-1,0))
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}
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}
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object LFSR16
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{
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def apply(increment: Bool = Bool(true)) =
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{
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val width = 16
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val lfsr = Reg(resetVal = UFix(1, width))
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when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)).toUFix }
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lfsr
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}
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}
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object ShiftRegister
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{
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def apply [T <: Data](n: Int, in: T): T =
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if (n > 0) Reg(apply(n-1, in)) else in
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}
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object Mux1H
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{
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def buildMux[T <: Data](sel: Bits, in: Seq[T], i: Int, n: Int): T = {
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if (n == 1)
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in(i)
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else
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{
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val half_n = (1 << log2up(n))/2
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val left = buildMux(sel, in, i, half_n)
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val right = buildMux(sel, in, i + half_n, n - half_n)
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Mux(sel(i+n-1,i+half_n).orR, right, left)
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}
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}
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def apply [T <: Data](sel: Bits, in: Seq[T]): T = buildMux(sel, in, 0, sel.getWidth)
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def apply [T <: Data](sel: Seq[Bool], in: Seq[T]): T = buildMux(Cat(Bits(0),sel.reverse:_*), in, 0, sel.size)
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}
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class Mux1H [T <: Data](n: Int)(gen: => T) extends Component
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{
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val io = new Bundle {
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@ -146,76 +26,6 @@ class Mux1H [T <: Data](n: Int)(gen: => T) extends Component
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io.out := Mux1H(io.sel, io.in)
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}
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class ioDecoupled[+T <: Data]()(data: => T) extends Bundle
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{
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val ready = Bool(INPUT)
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val valid = Bool(OUTPUT)
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val bits = data.asOutput
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}
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class ioPipe[+T <: Data]()(data: => T) extends Bundle
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{
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val valid = Bool(OUTPUT)
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val bits = data.asOutput
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}
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class ioArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
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val in = Vec(n) { (new ioDecoupled()) { data } }.flip
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val out = (new ioDecoupled()) { data }
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val chosen = Bits(log2up(n), OUTPUT)
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}
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object ArbiterCtrl
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{
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def apply(request: Seq[Bool]) = {
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Bool(true) +: (1 until request.length).map(i => !foldR(request.slice(0, i))(_||_))
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}
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}
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class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
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val io = new ioArbiter(n)(data)
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val grant = ArbiterCtrl(io.in.map(_.valid))
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(0 until n).map(i => io.in(i).ready := grant(i) && io.out.ready)
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var dout = io.in(n-1).bits
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var choose = Bits(n-1)
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for (i <- n-2 to 0 by -1) {
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dout = Mux(io.in(i).valid, io.in(i).bits, dout)
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choose = Mux(io.in(i).valid, Bits(i), choose)
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}
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io.out.valid := foldR(io.in.map(_.valid))(_||_)
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io.out.bits <> dout
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io.chosen := choose
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}
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class RRArbiter[T <: Data](n: Int)(data: => T) extends Component {
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val io = new ioArbiter(n)(data)
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val last_grant = Reg(resetVal = Bits(0, log2up(n)))
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val g = ArbiterCtrl((0 until n).map(i => io.in(i).valid && UFix(i) > last_grant) ++ io.in.map(_.valid))
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val grant = (0 until n).map(i => g(i) && UFix(i) > last_grant || g(i+n))
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(0 until n).map(i => io.in(i).ready := grant(i) && io.out.ready)
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var choose = Bits(n-1)
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for (i <- n-2 to 0 by -1)
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choose = Mux(io.in(i).valid, Bits(i), choose)
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for (i <- n-1 to 1 by -1)
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choose = Mux(io.in(i).valid && UFix(i) > last_grant, Bits(i), choose)
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when (io.out.valid && io.out.ready) {
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last_grant := choose
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}
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val dvec = Vec(n) { data }
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(0 until n).map(i => dvec(i) := io.in(i).bits )
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io.out.valid := foldR(io.in.map(_.valid))(_||_)
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io.out.bits := dvec(choose)
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io.chosen := choose
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}
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class ioLockingArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
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val in = Vec(n) { (new ioDecoupled()) { data } }.flip
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val lock = Vec(n) { Bool() }.asInput
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