From 04304fe788cf6162dc57834d248a7a4dd8c47fb7 Mon Sep 17 00:00:00 2001
From: Huy Vo <huytbvo@berkeley.edu>
Date: Wed, 6 Jun 2012 12:47:17 -0700
Subject: [PATCH] moving util out into Chisel standard library

---
 rocket/src/main/scala/arbiter.scala         |  12 +-
 rocket/src/main/scala/consts.scala          |   8 +-
 rocket/src/main/scala/cpu.scala             |   2 +-
 rocket/src/main/scala/ctrl_util.scala       |   4 +-
 rocket/src/main/scala/divider.scala         |   2 +-
 rocket/src/main/scala/dpath_util.scala      |   2 +-
 rocket/src/main/scala/dtlb.scala            |   2 +-
 rocket/src/main/scala/htif.scala            |  26 +--
 rocket/src/main/scala/icache.scala          |  12 +-
 rocket/src/main/scala/icache_prefetch.scala |   4 +-
 rocket/src/main/scala/itlb.scala            |   6 +-
 rocket/src/main/scala/memserdes.scala       |  12 +-
 rocket/src/main/scala/multiplier.scala      |   6 +-
 rocket/src/main/scala/nbdcache.scala        |  30 ++--
 rocket/src/main/scala/ptw.scala             |  10 +-
 rocket/src/main/scala/queues.scala          |   4 +-
 rocket/src/main/scala/slowio.scala          |   4 +-
 rocket/src/main/scala/uncore.scala          |  10 +-
 rocket/src/main/scala/util.scala            | 190 --------------------
 19 files changed, 78 insertions(+), 268 deletions(-)

diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala
index a96753dd..c4fce66c 100644
--- a/rocket/src/main/scala/arbiter.scala
+++ b/rocket/src/main/scala/arbiter.scala
@@ -28,12 +28,12 @@ class rocketMemArbiter(n: Int) extends Component {
 
   var xi_bits = new TransactionInit
   xi_bits := io.requestor(n-1).xact_init.bits
-  xi_bits.tile_xact_id := Cat(io.requestor(n-1).xact_init.bits.tile_xact_id, UFix(n-1, log2up(n)))
+  xi_bits.tile_xact_id := Cat(io.requestor(n-1).xact_init.bits.tile_xact_id, UFix(n-1, log2Up(n)))
   for (i <- n-2 to 0 by -1)
   {
     var my_xi_bits = new TransactionInit
     my_xi_bits := io.requestor(i).xact_init.bits
-    my_xi_bits.tile_xact_id := Cat(io.requestor(i).xact_init.bits.tile_xact_id, UFix(i, log2up(n)))
+    my_xi_bits.tile_xact_id := Cat(io.requestor(i).xact_init.bits.tile_xact_id, UFix(i, log2Up(n)))
 
     xi_bits = Mux(io.requestor(i).xact_init.valid, my_xi_bits, xi_bits)
   }
@@ -60,17 +60,17 @@ class rocketMemArbiter(n: Int) extends Component {
   for (i <- 0 until n)
   {
     val tag = io.mem.xact_rep.bits.tile_xact_id
-    io.requestor(i).xact_rep.valid := io.mem.xact_rep.valid && tag(log2up(n)-1,0) === UFix(i)
+    io.requestor(i).xact_rep.valid := io.mem.xact_rep.valid && tag(log2Up(n)-1,0) === UFix(i)
     io.requestor(i).xact_rep.bits := io.mem.xact_rep.bits
-    io.requestor(i).xact_rep.bits.tile_xact_id := tag >> UFix(log2up(n))
+    io.requestor(i).xact_rep.bits.tile_xact_id := tag >> UFix(log2Up(n))
   }
 
   for (i <- 0 until n)
   {
     val tag = io.mem.xact_abort.bits.tile_xact_id
-    io.requestor(i).xact_abort.valid := io.mem.xact_abort.valid && tag(log2up(n)-1,0) === UFix(i)
+    io.requestor(i).xact_abort.valid := io.mem.xact_abort.valid && tag(log2Up(n)-1,0) === UFix(i)
     io.requestor(i).xact_abort.bits := io.mem.xact_abort.bits
-    io.requestor(i).xact_abort.bits.tile_xact_id := tag >> UFix(log2up(n))
+    io.requestor(i).xact_abort.bits.tile_xact_id := tag >> UFix(log2Up(n))
   }
 
   io.mem.xact_abort.ready := Bool(true)
diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala
index 0cac1b92..32cefbe7 100644
--- a/rocket/src/main/scala/consts.scala
+++ b/rocket/src/main/scala/consts.scala
@@ -176,7 +176,7 @@ object Constants
   val DCACHE_PORTS = 3
   val CPU_DATA_BITS = 64;
   val CPU_TAG_BITS = 9;
-  val DCACHE_TAG_BITS = log2up(DCACHE_PORTS) + CPU_TAG_BITS
+  val DCACHE_TAG_BITS = log2Up(DCACHE_PORTS) + CPU_TAG_BITS
   val OFFSET_BITS = 6; // log2(cache line size in bytes)
   val NMSHR = if (HAVE_VEC) 4 else 2 // number of primary misses
   val NRPQ = 16; // number of secondary misses
@@ -192,9 +192,9 @@ object Constants
   val ENABLE_CLEAN_EXCLUSIVE = true
 
   val COHERENCE_DATA_BITS = (1 << OFFSET_BITS)*8 
-  val TILE_ID_BITS = log2up(NTILES)+1
-  val TILE_XACT_ID_BITS = log2up(NMSHR)+3
-  val GLOBAL_XACT_ID_BITS = log2up(NTILES*NMSHR)+1
+  val TILE_ID_BITS = log2Up(NTILES)+1
+  val TILE_XACT_ID_BITS = log2Up(NMSHR)+3
+  val GLOBAL_XACT_ID_BITS = log2Up(NTILES*NMSHR)+1
   val NGLOBAL_XACTS = 1 << GLOBAL_XACT_ID_BITS
 
   val X_INIT_TYPE_MAX_BITS = 2
diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala
index 0799b8e0..756476f6 100644
--- a/rocket/src/main/scala/cpu.scala
+++ b/rocket/src/main/scala/cpu.scala
@@ -31,7 +31,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
     vu = new vu()
     // cpu, vector prefetch, and vector use the DTLB
     val dtlbarb = new RRArbiter(3)({new ioDTLB_CPU_req_bundle()})
-    val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2up(3)))
+    val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2Up(3)))
     when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen }
 
     // tlb respones come out a cycle later
diff --git a/rocket/src/main/scala/ctrl_util.scala b/rocket/src/main/scala/ctrl_util.scala
index e74b748e..77d855bb 100644
--- a/rocket/src/main/scala/ctrl_util.scala
+++ b/rocket/src/main/scala/ctrl_util.scala
@@ -6,12 +6,12 @@ import Node._;
 class rocketCtrlSboard(entries: Int, nread: Int, nwrite: Int) extends Component
 {
   class read_port extends Bundle {
-    val addr = UFix(log2up(entries), INPUT)
+    val addr = UFix(log2Up(entries), INPUT)
     val data = Bool(OUTPUT)
   }
   class write_port extends Bundle {
     val en = Bool(INPUT)
-    val addr = UFix(log2up(entries), INPUT)
+    val addr = UFix(log2Up(entries), INPUT)
     val data = Bool(INPUT)
   }
 
diff --git a/rocket/src/main/scala/divider.scala b/rocket/src/main/scala/divider.scala
index 26fc42b8..b016ee04 100644
--- a/rocket/src/main/scala/divider.scala
+++ b/rocket/src/main/scala/divider.scala
@@ -66,7 +66,7 @@ class rocketDivider(width: Int) extends Component {
   val rhs_in = Cat(rhs_hi, io.req.bits.in1(width/2-1,0))
         
   when ((state === s_ready) && io.req.valid) {
-    count := UFix(0, log2up(width+1));
+    count := UFix(0, log2Up(width+1));
     half := (dw === DW_32);
     neg_quo := Bool(false);
     neg_rem := Bool(false);
diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala
index 2ca0f958..d93149fa 100644
--- a/rocket/src/main/scala/dpath_util.scala
+++ b/rocket/src/main/scala/dpath_util.scala
@@ -22,7 +22,7 @@ class rocketDpathBTB(entries: Int) extends Component
 {
   val io = new ioDpathBTB();
 
-  val repl_way = LFSR16(io.wen)(log2up(entries)-1,0) // TODO: pseudo-LRU
+  val repl_way = LFSR16(io.wen)(log2Up(entries)-1,0) // TODO: pseudo-LRU
 
   var hit_reduction = Bool(false)
   val hit = Bool()
diff --git a/rocket/src/main/scala/dtlb.scala b/rocket/src/main/scala/dtlb.scala
index f4208d24..6246e8ad 100644
--- a/rocket/src/main/scala/dtlb.scala
+++ b/rocket/src/main/scala/dtlb.scala
@@ -17,7 +17,7 @@ class ioDTLB_CPU_req_bundle extends Bundle
   val asid = Bits(width=ASID_BITS)
   val vpn  = Bits(width=VPN_BITS+1)
 }
-class ioDTLB_CPU_req extends hwacha.ioDecoupled()( { new ioDTLB_CPU_req_bundle() } )
+class ioDTLB_CPU_req extends ioDecoupled()( { new ioDTLB_CPU_req_bundle() } )
 
 class ioDTLB_CPU_resp extends Bundle
 {
diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala
index 726dc553..c7df3b69 100644
--- a/rocket/src/main/scala/htif.scala
+++ b/rocket/src/main/scala/htif.scala
@@ -28,7 +28,7 @@ class ioHTIF extends Bundle
   val debug = new ioDebug
   val pcr_req = (new ioDecoupled) { new PCRReq }.flip
   val pcr_rep = (new ioPipe) { Bits(width = 64) }
-  val ipi = (new ioDecoupled) { Bits(width = log2up(NTILES)) }
+  val ipi = (new ioDecoupled) { Bits(width = log2Up(NTILES)) }
 }
 
 class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends Component
@@ -43,7 +43,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
   val long_request_bits = 576
   require(short_request_bits % w == 0)
 
-  val rx_count_w = 13 + log2up(64) - log2up(w) // data size field is 12 bits
+  val rx_count_w = 13 + log2Up(64) - log2Up(w) // data size field is 12 bits
   val rx_count = Reg(resetVal = UFix(0,rx_count_w))
   val rx_shifter = Reg() { Bits(width = short_request_bits) }
   val rx_shifter_in = Cat(io.host.in.bits, rx_shifter(short_request_bits-1,w))
@@ -65,18 +65,18 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
     }
   }
 
-  val rx_word_count = (rx_count >> UFix(log2up(short_request_bits/w)))
-  val rx_word_done = io.host.in.valid && rx_count(log2up(short_request_bits/w)-1,0).andR
+  val rx_word_count = (rx_count >> UFix(log2Up(short_request_bits/w)))
+  val rx_word_done = io.host.in.valid && rx_count(log2Up(short_request_bits/w)-1,0).andR
   val packet_ram_depth = long_request_bits/short_request_bits-1
   val packet_ram = Vec(packet_ram_depth) { Reg() { Bits(width = short_request_bits) } }
   when (rx_word_done && io.host.in.ready) {
-    packet_ram(rx_word_count(log2up(packet_ram_depth)-1,0) - UFix(1)) := rx_shifter_in
+    packet_ram(rx_word_count(log2Up(packet_ram_depth)-1,0) - UFix(1)) := rx_shifter_in
   }
 
   val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() }
 
   val pcr_addr = addr(4,0)
-  val pcr_coreid = if (ncores == 1) UFix(0) else addr(20+log2up(ncores),20)
+  val pcr_coreid = if (ncores == 1) UFix(0) else addr(20+log2Up(ncores),20)
   val pcr_wdata = packet_ram(0)
 
   val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR
@@ -85,14 +85,14 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
              Bool(true)))
 
   val tx_count = Reg(resetVal = UFix(0, rx_count_w))
-  val tx_subword_count = tx_count(log2up(short_request_bits/w)-1,0)
-  val tx_word_count = tx_count(rx_count_w-1, log2up(short_request_bits/w))
-  val packet_ram_raddr = tx_word_count(log2up(packet_ram_depth)-1,0) - UFix(1)
+  val tx_subword_count = tx_count(log2Up(short_request_bits/w)-1,0)
+  val tx_word_count = tx_count(rx_count_w-1, log2Up(short_request_bits/w))
+  val packet_ram_raddr = tx_word_count(log2Up(packet_ram_depth)-1,0) - UFix(1)
   when (io.host.out.valid && io.host.out.ready) {
     tx_count := tx_count + UFix(1)
   }
 
-  val rx_done = rx_word_done && Mux(rx_word_count === UFix(0), next_cmd != cmd_writemem && next_cmd != cmd_writecr, rx_word_count === size || rx_word_count(log2up(packet_ram_depth)-1,0) === UFix(0))
+  val rx_done = rx_word_done && Mux(rx_word_count === UFix(0), next_cmd != cmd_writemem && next_cmd != cmd_writecr, rx_word_count === size || rx_word_count(log2Up(packet_ram_depth)-1,0) === UFix(0))
   val tx_size = Mux(!nack && (cmd === cmd_readmem || cmd === cmd_readcr), size, UFix(0))
   val tx_done = io.host.out.ready && tx_subword_count.andR && (tx_word_count === tx_size || tx_word_count > UFix(0) && packet_ram_raddr.andR)
 
@@ -122,7 +122,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
     state := state_tx
   }
 
-  val mem_cnt = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
+  val mem_cnt = Reg(resetVal = UFix(0, log2Up(REFILL_CYCLES)))
   when (state === state_mem_req && io.mem.xact_init.ready) {
     state := Mux(cmd === cmd_writemem, state_mem_wdata, state_mem_rdata)
   }
@@ -170,7 +170,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
 
   var mem_req_data: Bits = null
   for (i <- 0 until MEM_DATA_BITS/short_request_bits) {
-    val idx = Cat(mem_cnt, UFix(i, log2up(MEM_DATA_BITS/short_request_bits)))
+    val idx = Cat(mem_cnt, UFix(i, log2Up(MEM_DATA_BITS/short_request_bits)))
     when (state === state_mem_rdata && io.mem.xact_rep.valid) {
       packet_ram(idx) := io.mem.xact_rep.bits.data((i+1)*short_request_bits-1, i*short_request_bits)
     }
@@ -240,5 +240,5 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
 
   io.host.in.ready := state === state_rx
   io.host.out.valid := state === state_tx
-  io.host.out.bits := tx_data >> Cat(tx_count(log2up(short_request_bits/w)-1,0), Bits(0, log2up(w)))
+  io.host.out.bits := tx_data >> Cat(tx_count(log2Up(short_request_bits/w)-1,0), Bits(0, log2Up(w)))
 }
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 1fedc7da..3f6523d6 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -33,7 +33,7 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
 
   val lines = sets * assoc;
   val addrbits = PADDR_BITS;
-  val indexbits = log2up(sets);
+  val indexbits = log2Up(sets);
   val offsetbits = OFFSET_BITS;
   val tagmsb    = addrbits - 1;
   val taglsb    = indexbits+offsetbits;
@@ -42,11 +42,11 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
   val indexlsb  = offsetbits;
   val offsetmsb = indexlsb-1;
   val databits = 32;
-  val offsetlsb = log2up(databits/8);
-  val rf_cnt_bits = log2up(REFILL_CYCLES);
+  val offsetlsb = log2Up(databits/8);
+  val rf_cnt_bits = log2Up(REFILL_CYCLES);
 
   require(PGIDX_BITS >= taglsb); // virtually-indexed, physically-tagged constraint
-  require(ispow2(sets) && ispow2(assoc));
+  require(isPow2(sets) && isPow2(assoc));
   
   val s_reset :: s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(5) { UFix() };
   val state = Reg(resetVal = s_reset);
@@ -82,8 +82,8 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
   }
   val refill_done = io.mem.xact_rep.valid && refill_count.andR
 
-  val repl_way = if (assoc == 1) UFix(0) else LFSR16(state === s_ready && r_cpu_req_val && !io.cpu.itlb_miss && !tag_hit)(log2up(assoc)-1,0)
-  val word_shift = Cat(r_cpu_req_idx(offsetmsb-rf_cnt_bits,offsetlsb), UFix(0, log2up(databits))).toUFix
+  val repl_way = if (assoc == 1) UFix(0) else LFSR16(state === s_ready && r_cpu_req_val && !io.cpu.itlb_miss && !tag_hit)(log2Up(assoc)-1,0)
+  val word_shift = Cat(r_cpu_req_idx(offsetmsb-rf_cnt_bits,offsetlsb), UFix(0, log2Up(databits))).toUFix
   val tag_we = refill_done
   val tag_addr = 
     Mux((state === s_refill), r_cpu_req_idx(indexmsb,indexlsb),
diff --git a/rocket/src/main/scala/icache_prefetch.scala b/rocket/src/main/scala/icache_prefetch.scala
index 956dd08f..45ed9fc2 100644
--- a/rocket/src/main/scala/icache_prefetch.scala
+++ b/rocket/src/main/scala/icache_prefetch.scala
@@ -43,7 +43,7 @@ class rocketIPrefetcher(co: CoherencePolicyWithUncached) extends Component
   finish_arb.io.in(1) <> finish_q.io.deq
   io.mem.xact_finish <> finish_arb.io.out
   
-  val fill_cnt = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
+  val fill_cnt = Reg(resetVal = UFix(0, log2Up(REFILL_CYCLES)))
   when (ip_mem_resp_val) { fill_cnt := fill_cnt + UFix(1) }
   val fill_done = fill_cnt.andR && ip_mem_resp_val
 
@@ -51,7 +51,7 @@ class rocketIPrefetcher(co: CoherencePolicyWithUncached) extends Component
   finish_q.io.enq.bits.global_xact_id := io.mem.xact_rep.bits.global_xact_id
   
   val forward = Reg(resetVal = Bool(false))
-  val forward_cnt = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
+  val forward_cnt = Reg(resetVal = UFix(0, log2Up(REFILL_CYCLES)))
   when (forward && pdq.io.deq.valid) { forward_cnt := forward_cnt + UFix(1) }
   val forward_done = forward_cnt.andR && pdq.io.deq.valid
   forward := demand_miss && hit || forward && !forward_done
diff --git a/rocket/src/main/scala/itlb.scala b/rocket/src/main/scala/itlb.scala
index a14717a3..d11fc359 100644
--- a/rocket/src/main/scala/itlb.scala
+++ b/rocket/src/main/scala/itlb.scala
@@ -55,7 +55,7 @@ class PseudoLRU(n: Int)
   def access(way: UFix) = {
     var next_state = state
     var idx = UFix(1,1)
-    for (i <- log2up(n)-1 to 0 by -1) {
+    for (i <- log2Up(n)-1 to 0 by -1) {
       val bit = way(i)
       val mask = (UFix(1,n) << idx)(n-1,0)
       next_state = next_state & ~mask | Mux(bit, UFix(0), mask)
@@ -66,9 +66,9 @@ class PseudoLRU(n: Int)
   }
   def replace = {
     var idx = UFix(1,1)
-    for (i <- 0 until log2up(n))
+    for (i <- 0 until log2Up(n))
       idx = Cat(idx, state(idx))
-    idx(log2up(n)-1,0)
+    idx(log2Up(n)-1,0)
   }
 }
 
diff --git a/rocket/src/main/scala/memserdes.scala b/rocket/src/main/scala/memserdes.scala
index 27bbaa95..8dc6a8ae 100644
--- a/rocket/src/main/scala/memserdes.scala
+++ b/rocket/src/main/scala/memserdes.scala
@@ -26,8 +26,8 @@ class MemSerdes extends Component
 
   val s_idle :: s_read_addr :: s_write_addr :: s_write_idle :: s_write_data :: Nil = Enum(5) { UFix() }
   val state = Reg(resetVal = s_idle)
-  val send_cnt = Reg(resetVal = UFix(0, log2up((max(abits, dbits)+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH)))
-  val data_send_cnt = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
+  val send_cnt = Reg(resetVal = UFix(0, log2Up((max(abits, dbits)+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH)))
+  val data_send_cnt = Reg(resetVal = UFix(0, log2Up(REFILL_CYCLES)))
   val adone = io.narrow.req.ready && send_cnt === UFix((abits-1)/MEM_BACKUP_WIDTH)
   val ddone = io.narrow.req.ready && send_cnt === UFix((dbits-1)/MEM_BACKUP_WIDTH)
 
@@ -67,8 +67,8 @@ class MemSerdes extends Component
     send_cnt := UFix(0)
   }
 
-  val recv_cnt = Reg(resetVal = UFix(0, log2up((rbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH)))
-  val data_recv_cnt = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
+  val recv_cnt = Reg(resetVal = UFix(0, log2Up((rbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH)))
+  val data_recv_cnt = Reg(resetVal = UFix(0, log2Up(REFILL_CYCLES)))
   val resp_val = Reg(resetVal = Bool(false))
 
   resp_val := Bool(false)
@@ -98,8 +98,8 @@ class MemDessert extends Component // test rig side
   val rbits = io.wide.resp.bits.getWidth
 
   require(dbits >= abits && rbits >= dbits)
-  val recv_cnt = Reg(resetVal = UFix(0, log2up((rbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH)))
-  val data_recv_cnt = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
+  val recv_cnt = Reg(resetVal = UFix(0, log2Up((rbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH)))
+  val data_recv_cnt = Reg(resetVal = UFix(0, log2Up(REFILL_CYCLES)))
   val adone = io.narrow.req.valid && recv_cnt === UFix((abits-1)/MEM_BACKUP_WIDTH)
   val ddone = io.narrow.req.valid && recv_cnt === UFix((dbits-1)/MEM_BACKUP_WIDTH)
   val rdone = io.narrow.resp.valid && recv_cnt === UFix((rbits-1)/MEM_BACKUP_WIDTH)
diff --git a/rocket/src/main/scala/multiplier.scala b/rocket/src/main/scala/multiplier.scala
index a29ab658..a0e69332 100644
--- a/rocket/src/main/scala/multiplier.scala
+++ b/rocket/src/main/scala/multiplier.scala
@@ -26,7 +26,7 @@ class rocketVUMultiplier(nwbq: Int) extends Component {
   }
 
   val valid = Reg(resetVal = Bits(0, IMUL_STAGES))
-  val wbq_cnt = Reg(resetVal = Bits(0, log2up(nwbq+1)))
+  val wbq_cnt = Reg(resetVal = Bits(0, log2Up(nwbq+1)))
   val tag = Vec(IMUL_STAGES) { Reg() { Bits() } }
 
   val fire = io.cpu.req.valid && io.cpu.req.ready
@@ -80,7 +80,7 @@ class rocketMultiplier extends Component {
   val r_lhs = Reg { Bits() }
   val r_prod= Reg { Bits(width = w*2) }
   val r_lsb = Reg { Bits() }
-  val r_cnt = Reg { UFix(width = log2up(cycles+1)) }
+  val r_cnt = Reg { UFix(width = log2Up(cycles+1)) }
 
   val dw = io.req.bits.fn(io.req.bits.fn.width-1)
   val fn = io.req.bits.fn(io.req.bits.fn.width-2,0)
@@ -99,7 +99,7 @@ class rocketMultiplier extends Component {
   
   when (io.req.valid && io.req.ready) {
     r_val := Bool(true)
-    r_cnt := UFix(0, log2up(cycles+1))
+    r_cnt := UFix(0, log2Up(cycles+1))
     r_dw  := dw
     r_fn  := fn
     r_tag := io.req_tag
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index d0601fde..7c12a2cd 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -6,7 +6,7 @@ import Constants._
 class ioReplacementWayGen extends Bundle {
   val pick_new_way = Bool(dir = INPUT)
   val way_en = Bits(width = NWAYS, dir = INPUT)
-  val way_id = UFix(width = log2up(NWAYS), dir = OUTPUT)
+  val way_id = UFix(width = log2Up(NWAYS), dir = OUTPUT)
 }
 
 class RandomReplacementWayGen extends Component {
@@ -15,7 +15,7 @@ class RandomReplacementWayGen extends Component {
   io.way_id := UFix(0)
   if(NWAYS > 1) 
   {
-    val rand_way_id = LFSR16(io.pick_new_way)(log2up(NWAYS)-1,0)
+    val rand_way_id = LFSR16(io.pick_new_way)(log2Up(NWAYS)-1,0)
     when (rand_way_id < UFix(NWAYS)) { io.way_id := rand_way_id }
   }
 }
@@ -58,7 +58,7 @@ class StoreDataGen extends Component {
 class LoadDataGen extends Component {
   val io = new Bundle {
     val typ  = Bits(3, INPUT)
-    val addr = Bits(log2up(MEM_DATA_BITS/8), INPUT)
+    val addr = Bits(log2Up(MEM_DATA_BITS/8), INPUT)
     val din  = Bits(MEM_DATA_BITS, INPUT)
     val dout = Bits(64, OUTPUT)
     val r_dout = Bits(64, OUTPUT)
@@ -112,7 +112,7 @@ class RPQEntry extends Bundle {
   val offset = Bits(width = OFFSET_BITS)
   val cmd    = Bits(width = 4)
   val typ    = Bits(width = 3)
-  val sdq_id = UFix(width = log2up(NSDQ))
+  val sdq_id = UFix(width = log2Up(NSDQ))
   val cpu_tag = Bits(width = DCACHE_TAG_BITS)
 }
 
@@ -133,7 +133,7 @@ class DataReq extends Bundle {
 class DataArrayReq extends Bundle {
   val way_en = Bits(width = NWAYS)
   val idx    = Bits(width = IDX_BITS)
-  val offset = Bits(width = log2up(REFILL_CYCLES))
+  val offset = Bits(width = log2Up(REFILL_CYCLES))
   val rw     = Bool()
   val wmask  = Bits(width = MEM_DATA_BITS/8)
   val data   = Bits(width = MEM_DATA_BITS)
@@ -165,11 +165,11 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
     val req_sec_val    = Bool(INPUT)
     val req_sec_rdy    = Bool(OUTPUT)
     val req_bits       = new MSHRReq().asInput
-    val req_sdq_id     = UFix(log2up(NSDQ), INPUT)
+    val req_sdq_id     = UFix(log2Up(NSDQ), INPUT)
 
     val idx_match      = Bool(OUTPUT)
     val idx            = Bits(IDX_BITS, OUTPUT)
-    val refill_count   = Bits(log2up(REFILL_CYCLES), OUTPUT)
+    val refill_count   = Bits(log2Up(REFILL_CYCLES), OUTPUT)
     val tag            = Bits(TAG_BITS, OUTPUT)
     val way_oh         = Bits(NWAYS, OUTPUT)
 
@@ -190,7 +190,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
 
   val xacx_type = Reg { UFix() }
   val line_state = Reg { UFix() }
-  val refill_count = Reg { UFix(width = log2up(REFILL_CYCLES)) }
+  val refill_count = Reg { UFix(width = log2Up(REFILL_CYCLES)) }
   val req = Reg { new MSHRReq() }
 
   val req_cmd = io.req_bits.cmd
@@ -298,7 +298,7 @@ class MSHRFile(co: CoherencePolicy) extends Component {
     val secondary_miss = Bool(OUTPUT)
 
     val mem_resp_idx = Bits(IDX_BITS, OUTPUT)
-    val mem_resp_offset = Bits(log2up(REFILL_CYCLES), OUTPUT)
+    val mem_resp_offset = Bits(log2Up(REFILL_CYCLES), OUTPUT)
     val mem_resp_way_oh = Bits(NWAYS, OUTPUT)
 
     val fence_rdy = Bool(OUTPUT)
@@ -429,7 +429,7 @@ class WritebackUnit(co: CoherencePolicy) extends Component {
   val is_probe = Reg() { Bool() }
   val data_req_fired = Reg(resetVal = Bool(false))
   val cmd_sent = Reg() { Bool() }
-  val cnt = Reg() { UFix(width = log2up(REFILL_CYCLES+1)) }
+  val cnt = Reg() { UFix(width = log2Up(REFILL_CYCLES+1)) }
   val req = Reg() { new WritebackReq() }
 
   val dout_rdy = Mux(is_probe, io.probe_rep_data.ready, io.mem_req_data.ready)
@@ -555,9 +555,9 @@ class FlushUnit(lines: Int, co: CoherencePolicy) extends Component {
   
   val s_reset :: s_ready :: s_meta_read :: s_meta_wait :: Nil = Enum(4) { UFix() }
   val state = Reg(resetVal = s_reset)
-  val idx_cnt = Reg(resetVal = UFix(0, log2up(lines)))
+  val idx_cnt = Reg(resetVal = UFix(0, log2Up(lines)))
   val next_idx_cnt = idx_cnt + UFix(1)
-  val way_cnt = if (NWAYS == 1) UFix(0) else Reg(resetVal = UFix(0, log2up(NWAYS)))
+  val way_cnt = if (NWAYS == 1) UFix(0) else Reg(resetVal = UFix(0, log2Up(NWAYS)))
   val next_way_cnt = way_cnt + UFix(1)
 
   switch (state) {
@@ -777,8 +777,8 @@ class HellaCache(co: CoherencePolicy) extends Component {
   val indexmsb    = taglsb-1
   val indexlsb    = offsetbits
   val offsetmsb   = indexlsb-1
-  val offsetlsb   = log2up(CPU_DATA_BITS/8)
-  val ramindexlsb = log2up(MEM_DATA_BITS/8)
+  val offsetlsb   = log2Up(CPU_DATA_BITS/8)
+  val ramindexlsb = log2Up(MEM_DATA_BITS/8)
   
   val early_nack       = Reg { Bool() }
   val r_cpu_req_val_   = Reg(io.cpu.req.valid && io.cpu.req.ready, resetVal = Bool(false))
@@ -1008,7 +1008,7 @@ class HellaCache(co: CoherencePolicy) extends Component {
   val store_offset = Mux(!replay_fire, p_store_idx(offsetmsb,0), replay.offset)
   maskgen.io.typ := Mux(!replay_fire, p_store_type, replay.typ)
   maskgen.io.addr := store_offset(offsetlsb-1,0)
-  val store_wmask_wide = maskgen.io.wmask << Cat(store_offset(ramindexlsb-1,offsetlsb), Bits(0, log2up(CPU_DATA_BITS/8))).toUFix
+  val store_wmask_wide = maskgen.io.wmask << Cat(store_offset(ramindexlsb-1,offsetlsb), Bits(0, log2Up(CPU_DATA_BITS/8))).toUFix
   val store_data = Mux(!replay_fire, p_store_data, replay.data)
   val store_data_wide = Fill(MEM_DATA_BITS/CPU_DATA_BITS, store_data)
   data_arb.io.in(1).bits.data := store_data_wide
diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala
index 38364c85..f1d05e06 100644
--- a/rocket/src/main/scala/ptw.scala
+++ b/rocket/src/main/scala/ptw.scala
@@ -14,7 +14,7 @@ class ioHellaCacheArbiter(n: Int) extends Bundle
 class rocketHellaCacheArbiter(n: Int) extends Component
 {
   val io = new ioHellaCacheArbiter(n)
-  require(DCACHE_TAG_BITS >= log2up(n) + CPU_TAG_BITS)
+  require(DCACHE_TAG_BITS >= log2Up(n) + CPU_TAG_BITS)
 
   var req_val = Bool(false)
   var req_rdy = io.mem.req.ready
@@ -41,7 +41,7 @@ class rocketHellaCacheArbiter(n: Int) extends Component
     req_ppn  = Mux(Reg(r.valid), r.bits.ppn, req_ppn)
     req_data = Mux(Reg(r.valid), r.bits.data, req_data)
     req_kill = Mux(Reg(r.valid), r.bits.kill, req_kill)
-    req_tag  = Mux(r.valid, Cat(r.bits.tag, UFix(i, log2up(n))), req_tag)
+    req_tag  = Mux(r.valid, Cat(r.bits.tag, UFix(i, log2Up(n))), req_tag)
   }
 
   io.mem.req.valid     := req_val
@@ -57,7 +57,7 @@ class rocketHellaCacheArbiter(n: Int) extends Component
   {
     val r = io.requestor(i).resp
     val x = io.requestor(i).xcpt
-    val tag_hit = io.mem.resp.bits.tag(log2up(n)-1,0) === UFix(i)
+    val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === UFix(i)
     x.ma.ld := io.mem.xcpt.ma.ld && Reg(io.requestor(i).req.valid)
     x.ma.st := io.mem.xcpt.ma.st && Reg(io.requestor(i).req.valid)
     r.valid             := io.mem.resp.valid && tag_hit
@@ -67,7 +67,7 @@ class rocketHellaCacheArbiter(n: Int) extends Component
     r.bits.data         := io.mem.resp.bits.data
     r.bits.data_subword := io.mem.resp.bits.data_subword
     r.bits.typ          := io.mem.resp.bits.typ
-    r.bits.tag          := io.mem.resp.bits.tag >> UFix(log2up(n))
+    r.bits.tag          := io.mem.resp.bits.tag >> UFix(log2Up(n))
   }
 }
 
@@ -86,7 +86,7 @@ class rocketPTW(n: Int) extends Component
   val bitsPerLevel = VPN_BITS/levels
   require(VPN_BITS == levels * bitsPerLevel)
 
-  val count = Reg() { UFix(width = log2up(levels)) }
+  val count = Reg() { UFix(width = log2Up(levels)) }
   val s_ready :: s_req :: s_wait :: s_done :: s_error :: Nil = Enum(5) { UFix() };
   val state = Reg(resetVal = s_ready);
   
diff --git a/rocket/src/main/scala/queues.scala b/rocket/src/main/scala/queues.scala
index 44af8ff8..12bf1d22 100644
--- a/rocket/src/main/scala/queues.scala
+++ b/rocket/src/main/scala/queues.scala
@@ -22,8 +22,8 @@ class queue[T <: Data](entries: Int, pipe: Boolean = false, flushable: Boolean =
 
   if (entries > 1)
   {
-    enq_ptr = Reg(resetVal = UFix(0, log2up(entries)))
-    deq_ptr = Reg(resetVal = UFix(0, log2up(entries)))
+    enq_ptr = Reg(resetVal = UFix(0, log2Up(entries)))
+    deq_ptr = Reg(resetVal = UFix(0, log2Up(entries)))
     val pow2 = Bool((entries & (entries-1)) == 0)
 
     when (do_deq) {
diff --git a/rocket/src/main/scala/slowio.scala b/rocket/src/main/scala/slowio.scala
index e54996ef..0c513849 100644
--- a/rocket/src/main/scala/slowio.scala
+++ b/rocket/src/main/scala/slowio.scala
@@ -19,7 +19,7 @@ class slowIO[T <: Data](val divisor: Int, hold_cycles_in: Int = -1)(data: => T)
   require((divisor & (divisor-1)) == 0)
   require(hold_cycles < divisor/2 && hold_cycles >= 1)
 
-  val cnt = Reg() { UFix(width = log2up(divisor)) }
+  val cnt = Reg() { UFix(width = log2Up(divisor)) }
   cnt := cnt + UFix(1)
   val out_en = cnt === UFix(divisor/2+hold_cycles-1) // rising edge + hold time
   val in_en = cnt === UFix(divisor/2-1) // rising edge
@@ -46,5 +46,5 @@ class slowIO[T <: Data](val divisor: Int, hold_cycles_in: Int = -1)(data: => T)
   io.in_slow.ready := in_slow_rdy
   io.out_slow.valid := out_slow_val
   io.out_slow.bits := out_slow_bits
-  io.clk_slow := cnt(log2up(divisor)-1).toBool
+  io.clk_slow := cnt(log2Up(divisor)-1).toBool
 }
diff --git a/rocket/src/main/scala/uncore.scala b/rocket/src/main/scala/uncore.scala
index ab56d0f4..9791ea0f 100644
--- a/rocket/src/main/scala/uncore.scala
+++ b/rocket/src/main/scala/uncore.scala
@@ -120,7 +120,7 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
   val x_type_ = Reg{ Bits() }
   val init_tile_id_ = Reg{ Bits() }
   val tile_xact_id_ = Reg{ Bits() }
-  val p_rep_count = if (ntiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2up(ntiles)))
+  val p_rep_count = if (ntiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(ntiles)))
   val p_req_flags = Reg(resetVal = Bits(0, width = ntiles))
   val p_rep_tile_id_ = Reg{ Bits() }
   val x_needs_read = Reg(resetVal = Bool(false))
@@ -128,9 +128,9 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
   val p_rep_data_needs_write = Reg(resetVal = Bool(false))
   val x_w_mem_cmd_sent = Reg(resetVal = Bool(false))
   val p_w_mem_cmd_sent = Reg(resetVal = Bool(false))
-  val mem_cnt = Reg(resetVal = UFix(0, width = log2up(REFILL_CYCLES)))
+  val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
   val mem_cnt_next = mem_cnt + UFix(1)
-  val mem_cnt_max = ~UFix(0, width = log2up(REFILL_CYCLES))
+  val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES))
 
   io.busy := state != s_idle
   io.addr := addr_
@@ -415,7 +415,7 @@ class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceH
     val x_init = io.tiles(j).xact_init
     val x_init_data = io.tiles(j).xact_init_data
     val x_abort  = io.tiles(j).xact_abort
-    val abort_cnt = Reg(resetVal = UFix(0, width = log2up(REFILL_CYCLES)))
+    val abort_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
     val conflicts = Vec(NGLOBAL_XACTS) { Bool() }
     for( i <- 0 until NGLOBAL_XACTS) {
       val t = trackerList(i).io
@@ -438,7 +438,7 @@ class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceH
       is(s_abort_drain) { // raises x_init_data.ready below
         when(x_init_data.valid) {
           abort_cnt := abort_cnt + UFix(1)
-          when(abort_cnt === ~UFix(0, width = log2up(REFILL_CYCLES))) {
+          when(abort_cnt === ~UFix(0, width = log2Up(REFILL_CYCLES))) {
             abort_state_arr(j) := s_abort_send
           }
         }
diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala
index b01008ad..0eb6b190 100644
--- a/rocket/src/main/scala/util.scala
+++ b/rocket/src/main/scala/util.scala
@@ -4,23 +4,6 @@ import Chisel._
 import Node._
 import scala.math._
 
-
-object foldR
-{
-  def apply[T <: Bits](x: Seq[T])(f: (T, T) => T): T =
-    if (x.length == 1) x(0) else f(x(0), foldR(x.slice(1, x.length))(f))
-}
-
-object log2up
-{
-  def apply(in: Int) = ceil(log(in)/log(2)).toInt
-}
-
-object ispow2
-{
-  def apply(in: Int) = in > 0 && ((in & (in-1)) == 0)
-}
-
 object FillInterleaved
 {
   def apply(n: Int, in: Bits) =
@@ -32,109 +15,6 @@ object FillInterleaved
   }
 }
 
-// http://aggregate.ee.engr.uky.edu/MAGIC/#Population%20Count%20%28Ones%20Count%29
-// http://bits.stephan-brumme.com/countBits.html
-object PopCount
-{
-  def apply(in: Bits) =
-  {
-    require(in.width <= 32)
-    val w = log2up(in.width+1)
-    var x = in
-    if(in.width == 2) { 
-      x = x - ((x >> UFix(1)) & Bits("h_5555_5555"))
-    } else if(in.width <= 4) {
-      x = x - ((x >> UFix(1)) & Bits("h_5555_5555"))
-      x = (((x >> UFix(2)) & Bits("h_3333_3333")) + (x & Bits("h_3333_3333")))
-    } else if(in.width <= 8) {
-      x = x - ((x >> UFix(1)) & Bits("h_5555_5555"))
-      x = (((x >> UFix(2)) & Bits("h_3333_3333")) + (x & Bits("h_3333_3333")))
-      x = ((x >> UFix(4)) + x) 
-    } else {
-      // count bits of each 2-bit chunk
-      x = x - ((x >> UFix(1)) & Bits("h_5555_5555"))
-      // count bits of each 4-bit chunk
-      x = (((x >> UFix(2)) & Bits("h_3333_3333")) + (x & Bits("h_3333_3333")))
-      // count bits of each 8-bit chunk
-      x = ((x >> UFix(4)) + x) 
-      // mask junk in upper bits
-      x = x & Bits("h_0f0f_0f0f")
-      // add all four 8-bit chunks
-      x = x + (x >> UFix(8))
-      x = x + (x >> UFix(16))
-    }
-    x(w-1,0)
-  }
-}
-
-object Reverse
-{
-  def doit(in: Bits, base: Int, length: Int): Bits =
-  {
-    val half = (1 << log2up(length))/2
-    if (length == 1)
-      in(base)
-    else
-      Cat(doit(in, base, half), doit(in, base+half, length-half))
-  }
-  def apply(in: Bits) = doit(in, 0, in.getWidth)
-}
-
-object OHToUFix
-{
-  def apply(in: Seq[Bits]): UFix = {
-    if (in.size <= 1) return UFix(0)
-    if (in.size == 2) return in(1)
-    val hi = in.slice(in.size/2, in.size)
-    val lo = in.slice(0, in.size/2)
-    Cat(hi.reduceLeft(_||_), apply(hi zip lo map { case (x, y) => x || y }))
-  }
-  def apply(in: Bits): UFix = apply((0 until in.getWidth).map(in(_)))
-}
-
-object UFixToOH
-{
-  def apply(in: UFix, width: Int): Bits =
-  {
-    (UFix(1) << in(log2up(width)-1,0))
-  }
-}
-
-object LFSR16
-{
-  def apply(increment: Bool = Bool(true)) =
-  {
-    val width = 16
-    val lfsr = Reg(resetVal = UFix(1, width))
-    when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)).toUFix }
-    lfsr
-  }
-}
-
-object ShiftRegister
-{
-  def apply [T <: Data](n: Int, in: T): T =
-    if (n > 0) Reg(apply(n-1, in)) else in
-}
-
-object Mux1H 
-{
-  def buildMux[T <: Data](sel: Bits, in: Seq[T], i: Int, n: Int): T = {
-    if (n == 1)
-      in(i)
-    else
-    {
-      val half_n = (1 << log2up(n))/2
-      val left = buildMux(sel, in, i, half_n)
-      val right = buildMux(sel, in, i + half_n, n - half_n)
-      Mux(sel(i+n-1,i+half_n).orR, right, left)
-    }
-  }
-
-  def apply [T <: Data](sel: Bits, in: Seq[T]): T = buildMux(sel, in, 0, sel.getWidth)
-  def apply [T <: Data](sel: Seq[Bool], in: Seq[T]): T = buildMux(Cat(Bits(0),sel.reverse:_*), in, 0, sel.size)
-}
-
 class Mux1H [T <: Data](n: Int)(gen: => T) extends Component
 {
   val io = new Bundle {
@@ -146,76 +26,6 @@ class Mux1H [T <: Data](n: Int)(gen: => T) extends Component
   io.out := Mux1H(io.sel, io.in)
 }
 
-
-class ioDecoupled[+T <: Data]()(data: => T) extends Bundle
-{
-  val ready = Bool(INPUT)
-  val valid = Bool(OUTPUT)
-  val bits  = data.asOutput
-}
-
-class ioPipe[+T <: Data]()(data: => T) extends Bundle
-{
-  val valid = Bool(OUTPUT)
-  val bits = data.asOutput
-}
-
-class ioArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
-  val in  = Vec(n) { (new ioDecoupled()) { data } }.flip
-  val out = (new ioDecoupled()) { data }
-  val chosen = Bits(log2up(n), OUTPUT)
-}
-
-object ArbiterCtrl
-{
-  def apply(request: Seq[Bool]) = {
-    Bool(true) +: (1 until request.length).map(i => !foldR(request.slice(0, i))(_||_))
-  }
-}
-
-class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
-  val io = new ioArbiter(n)(data)
-
-  val grant = ArbiterCtrl(io.in.map(_.valid))
-  (0 until n).map(i => io.in(i).ready := grant(i) && io.out.ready)
-
-  var dout = io.in(n-1).bits
-  var choose = Bits(n-1)
-  for (i <- n-2 to 0 by -1) {
-    dout = Mux(io.in(i).valid, io.in(i).bits, dout)
-    choose = Mux(io.in(i).valid, Bits(i), choose)
-  }
-
-  io.out.valid := foldR(io.in.map(_.valid))(_||_)
-  io.out.bits <> dout
-  io.chosen := choose
-}
-
-class RRArbiter[T <: Data](n: Int)(data: => T) extends Component {
-  val io = new ioArbiter(n)(data)
-
-  val last_grant = Reg(resetVal = Bits(0, log2up(n)))
-  val g = ArbiterCtrl((0 until n).map(i => io.in(i).valid && UFix(i) > last_grant) ++ io.in.map(_.valid))
-  val grant = (0 until n).map(i => g(i) && UFix(i) > last_grant || g(i+n))
-  (0 until n).map(i => io.in(i).ready := grant(i) && io.out.ready)
-
-  var choose = Bits(n-1)
-  for (i <- n-2 to 0 by -1)
-    choose = Mux(io.in(i).valid, Bits(i), choose)
-  for (i <- n-1 to 1 by -1)
-    choose = Mux(io.in(i).valid && UFix(i) > last_grant, Bits(i), choose)
-  when (io.out.valid && io.out.ready) {
-    last_grant := choose
-  }
-
-  val dvec = Vec(n) { data } 
-  (0 until n).map(i => dvec(i) := io.in(i).bits )
-
-  io.out.valid := foldR(io.in.map(_.valid))(_||_)
-  io.out.bits := dvec(choose)
-  io.chosen := choose
-}
-
 class ioLockingArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
   val in   = Vec(n) { (new ioDecoupled()) { data } }.flip
   val lock = Vec(n) { Bool() }.asInput