moving util out into Chisel standard library
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@ -14,7 +14,7 @@ class ioHellaCacheArbiter(n: Int) extends Bundle
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class rocketHellaCacheArbiter(n: Int) extends Component
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{
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val io = new ioHellaCacheArbiter(n)
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require(DCACHE_TAG_BITS >= log2up(n) + CPU_TAG_BITS)
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require(DCACHE_TAG_BITS >= log2Up(n) + CPU_TAG_BITS)
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var req_val = Bool(false)
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var req_rdy = io.mem.req.ready
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@ -41,7 +41,7 @@ class rocketHellaCacheArbiter(n: Int) extends Component
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req_ppn = Mux(Reg(r.valid), r.bits.ppn, req_ppn)
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req_data = Mux(Reg(r.valid), r.bits.data, req_data)
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req_kill = Mux(Reg(r.valid), r.bits.kill, req_kill)
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req_tag = Mux(r.valid, Cat(r.bits.tag, UFix(i, log2up(n))), req_tag)
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req_tag = Mux(r.valid, Cat(r.bits.tag, UFix(i, log2Up(n))), req_tag)
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}
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io.mem.req.valid := req_val
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@ -57,7 +57,7 @@ class rocketHellaCacheArbiter(n: Int) extends Component
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{
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val r = io.requestor(i).resp
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val x = io.requestor(i).xcpt
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val tag_hit = io.mem.resp.bits.tag(log2up(n)-1,0) === UFix(i)
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val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === UFix(i)
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x.ma.ld := io.mem.xcpt.ma.ld && Reg(io.requestor(i).req.valid)
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x.ma.st := io.mem.xcpt.ma.st && Reg(io.requestor(i).req.valid)
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r.valid := io.mem.resp.valid && tag_hit
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@ -67,7 +67,7 @@ class rocketHellaCacheArbiter(n: Int) extends Component
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r.bits.data := io.mem.resp.bits.data
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r.bits.data_subword := io.mem.resp.bits.data_subword
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r.bits.typ := io.mem.resp.bits.typ
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r.bits.tag := io.mem.resp.bits.tag >> UFix(log2up(n))
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r.bits.tag := io.mem.resp.bits.tag >> UFix(log2Up(n))
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}
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}
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@ -86,7 +86,7 @@ class rocketPTW(n: Int) extends Component
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val bitsPerLevel = VPN_BITS/levels
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require(VPN_BITS == levels * bitsPerLevel)
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val count = Reg() { UFix(width = log2up(levels)) }
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val count = Reg() { UFix(width = log2Up(levels)) }
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val s_ready :: s_req :: s_wait :: s_done :: s_error :: Nil = Enum(5) { UFix() };
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val state = Reg(resetVal = s_ready);
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