From 02f89fb53030eaaee06b82e1d8c9fe1e9a6a57cf Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sun, 2 Oct 2016 00:31:14 -0700 Subject: [PATCH] RegMapper: clarify interface is DecoupledIO --- src/main/scala/uncore/tilelink2/RegMapper.scala | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/RegMapper.scala b/src/main/scala/uncore/tilelink2/RegMapper.scala index 3d14560d..0c3b4f9c 100644 --- a/src/main/scala/uncore/tilelink2/RegMapper.scala +++ b/src/main/scala/uncore/tilelink2/RegMapper.scala @@ -3,7 +3,6 @@ package uncore.tilelink2 import Chisel._ -import chisel3.util.{Irrevocable, IrrevocableIO} // A bus agnostic register interface to a register-based device @@ -52,8 +51,8 @@ object RegMapper val inBits = inParams.indexBits assert (wordmap.keySet.max < (1 << inBits), "Register map does not fit in device") - val out = Wire(Irrevocable(new RegMapperOutput(inParams))) - val front = Wire(Irrevocable(new RegMapperInput(inParams))) + val out = Wire(Decoupled(new RegMapperOutput(inParams))) + val front = Wire(Decoupled(new RegMapperInput(inParams))) front.bits := in.bits // Must this device pipeline the control channel?