2013-07-25 08:28:43 +02:00
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package referencechip
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import Chisel._
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import uncore._
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import scala.reflect._
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2014-01-21 21:37:47 +01:00
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import scala.reflect.runtime.universe._
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2013-07-25 08:28:43 +02:00
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2014-03-30 17:13:05 +02:00
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object TileLinkHeaderOverwriter {
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def apply[T <: ClientSourcedMessage](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int)(implicit conf: TileLinkConfiguration): DecoupledIO[LogicalNetworkIO[T]] = {
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val out = in.clone.asDirectionless
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out.bits.payload := in.bits.payload
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out.bits.header.src := UInt(clientId)
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out.bits.header.dst := in.bits.header.dst
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out.valid := in.valid
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in.ready := out.ready
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out
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2013-07-25 08:28:43 +02:00
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}
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2014-03-30 17:13:05 +02:00
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def apply[T <: ClientSourcedMessage with HasPhysicalAddress](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: UInt => UInt)(implicit conf: TileLinkConfiguration): DecoupledIO[LogicalNetworkIO[T]] = {
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val out: DecoupledIO[LogicalNetworkIO[T]] = apply(in, clientId)
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out.bits.header.dst := (if(nBanks > 1) addrConvert(in.bits.payload.addr) else UInt(0))
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out
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2013-07-25 08:28:43 +02:00
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}
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}
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2014-01-21 21:37:47 +01:00
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class ReferenceChipCrossbarNetwork(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO]()(conf.tl.ln) {
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2013-08-03 00:02:09 +02:00
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implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
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2014-01-21 21:37:47 +01:00
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val io = new Bundle {
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val clients = Vec.fill(ln.nClients){(new TileLinkIO).flip}
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val masters = Vec.fill(ln.nMasters){new TileLinkIO}
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}
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2014-03-30 17:13:05 +02:00
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2013-08-03 00:02:09 +02:00
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implicit val pconf = new PhysicalNetworkConfiguration(ln.nEndpoints, ln.idBits) // Same config for all networks
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2013-07-25 08:28:43 +02:00
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2014-01-21 21:37:47 +01:00
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// Actually instantiate the particular networks required for TileLink
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2014-03-30 17:13:05 +02:00
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val acqNet = Module(new BasicCrossbar(new Acquire))
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val relNet = Module(new BasicCrossbar(new Release))
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val prbNet = Module(new BasicCrossbar(new Probe))
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val gntNet = Module(new BasicCrossbar(new Grant))
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2014-01-21 21:37:47 +01:00
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val ackNet = Module(new BasicCrossbar(new GrantAck))
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2013-07-25 08:28:43 +02:00
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// Aliases for the various network IO bundle types
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2013-08-12 19:46:22 +02:00
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type FBCIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]]
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type FLNIO[T <: Data] = DecoupledIO[LogicalNetworkIO[T]]
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2013-07-25 08:28:43 +02:00
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type FromCrossbar[T <: Data] = FBCIO[T] => FLNIO[T]
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type ToCrossbar[T <: Data] = FLNIO[T] => FBCIO[T]
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// Shims for converting between logical network IOs and physical network IOs
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//TODO: Could be less verbose if you could override subbundles after a <>
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def DefaultFromCrossbarShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
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2013-09-11 01:23:52 +02:00
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val out = Decoupled(new LogicalNetworkIO(in.bits.payload)).asDirectionless
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2013-07-25 08:28:43 +02:00
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out.bits.header := in.bits.header
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out.bits.payload := in.bits.payload
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out.valid := in.valid
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in.ready := out.ready
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out
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}
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def CrossbarToMasterShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
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val out = DefaultFromCrossbarShim(in)
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2013-08-12 19:46:22 +02:00
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out.bits.header.src := in.bits.header.src - UInt(ln.nMasters)
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2013-07-25 08:28:43 +02:00
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out
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}
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def CrossbarToClientShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
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val out = DefaultFromCrossbarShim(in)
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2013-08-12 19:46:22 +02:00
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out.bits.header.dst := in.bits.header.dst - UInt(ln.nMasters)
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2013-07-25 08:28:43 +02:00
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out
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}
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def DefaultToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
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2013-09-11 01:23:52 +02:00
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val out = Decoupled(new PhysicalNetworkIO(in.bits.payload)).asDirectionless
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2013-07-25 08:28:43 +02:00
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out.bits.header := in.bits.header
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out.bits.payload := in.bits.payload
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out.valid := in.valid
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in.ready := out.ready
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out
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}
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def MasterToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
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val out = DefaultToCrossbarShim(in)
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2013-08-12 19:46:22 +02:00
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out.bits.header.dst := in.bits.header.dst + UInt(ln.nMasters)
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2013-07-25 08:28:43 +02:00
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out
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}
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def ClientToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
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val out = DefaultToCrossbarShim(in)
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2013-08-12 19:46:22 +02:00
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out.bits.header.src := in.bits.header.src + UInt(ln.nMasters)
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2013-07-25 08:28:43 +02:00
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out
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}
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// Make an individual connection between virtual and physical ports using
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// a particular shim. Also seal the unused FIFO control signal.
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def doFIFOInputHookup[T <: Data](phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], shim: ToCrossbar[T]) = {
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val s = shim(log_io)
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phys_in.valid := s.valid
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phys_in.bits := s.bits
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s.ready := phys_in.ready
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phys_out.ready := Bool(false)
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}
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def doFIFOOutputHookup[T <: Data](phys_in: FBCIO[T], phys_out: FBCIO[T], log_io: FLNIO[T], shim: FromCrossbar[T]) = {
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val s = shim(phys_out)
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log_io.valid := s.valid
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log_io.bits := s.bits
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s.ready := log_io.ready
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phys_in.valid := Bool(false)
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}
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2014-01-21 21:37:47 +01:00
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def doFIFOHookup[T <: Data](isEndpointSourceOfMessage: Boolean, physIn: FBCIO[T], physOut: FBCIO[T], logIO: FLNIO[T], inShim: ToCrossbar[T], outShim: FromCrossbar[T]) = {
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if(isEndpointSourceOfMessage) doFIFOInputHookup(physIn, physOut, logIO, inShim)
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2014-03-30 17:13:05 +02:00
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else doFIFOOutputHookup(physIn, physOut, logIO, outShim)
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2013-07-25 08:28:43 +02:00
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}
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2014-03-30 17:13:05 +02:00
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//Hookup all instances of a particular subbundle of TileLink
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2014-01-21 21:37:47 +01:00
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def doFIFOHookups[T <: Data: TypeTag](physIO: BasicCrossbarIO[T], getLogIO: TileLinkIO => FLNIO[T]) = {
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typeTag[T].tpe match{
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case t if t <:< typeTag[ClientSourcedMessage].tpe => {
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io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id), physIO.out(id), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) }
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io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) }
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}
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case t if t <:< typeTag[MasterSourcedMessage].tpe => {
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io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id), physIO.out(id), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) }
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io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) }
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}
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case _ => require(false, "Unknown message sourcing.")
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2013-07-25 08:28:43 +02:00
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}
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}
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2014-03-30 17:13:05 +02:00
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doFIFOHookups(acqNet.io, (tl: TileLinkIO) => tl.acquire)
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doFIFOHookups(relNet.io, (tl: TileLinkIO) => tl.release)
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doFIFOHookups(prbNet.io, (tl: TileLinkIO) => tl.probe)
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doFIFOHookups(gntNet.io, (tl: TileLinkIO) => tl.grant)
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2014-01-21 21:37:47 +01:00
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doFIFOHookups(ackNet.io, (tl: TileLinkIO) => tl.grant_ack)
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2013-07-25 08:28:43 +02:00
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}
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