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rocket-chip/src/main/scala/subsystem/PeripheryBus.scala

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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.subsystem
import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
case class PeripheryBusParams(
beatBytes: Int,
blockBytes: Int,
frequency: BigInt = BigInt(100000000) // 100 MHz as default bus frequency
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) extends HasTLBusParams
case object PeripheryBusKey extends Field[PeripheryBusParams]
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class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCrossing = SynchronousCrossing())
(implicit p: Parameters) extends TLBusWrapper(params, "PeripheryBus")
with HasTLXbarPhy
with HasCrossing {
private def bufferTo(buffer: BufferParams): TLOutwardNode =
TLBuffer(buffer) :*= delayNode :*= outwardNode
private def fragmentTo(minSize: Int, maxSize: Int, buffer: BufferParams): TLOutwardNode =
TLFragmenter(minSize, maxSize) :*= bufferTo(buffer)
private def fixedWidthTo(buffer: BufferParams): TLOutwardNode =
TLWidthWidget(params.beatBytes) :*= bufferTo(buffer)
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def toSlave(
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = {
to(s"Slave${name.getOrElse("")}") { gen :*= bufferTo(buffer) }
}
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def toVariableWidthSlave(
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = {
to(s"Slave${name.getOrElse("")}") {
gen :*= fragmentTo(params.beatBytes, params.blockBytes, buffer)
}
}
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def toFixedWidthSlave(
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = {
to(s"Slave${name.getOrElse("")}") {
gen :*= fixedWidthTo(buffer)
}
}
def toFixedWidthSingleBeatSlave(
widthBytes: Int,
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = {
to(s"Slave${name.getOrElse("")}") {
gen :*= TLFragmenter(widthBytes, params.blockBytes) :*= fixedWidthTo(buffer)
}
}
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def toLargeBurstSlave(
maxXferBytes: Int,
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = {
to(s"Slave${name.getOrElse("")}") {
gen :*= fragmentTo(params.beatBytes, maxXferBytes, buffer)
}
}
def fromSystemBus(
arithmetic: Boolean = true,
buffer: BufferParams = BufferParams.default)
(gen: => TLOutwardNode) {
from("SystemBus") {
(inwardNode
:*= TLBuffer(buffer)
:*= TLAtomicAutomata(arithmetic = arithmetic)
:*= gen)
}
}
def fromOtherMaster(
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLInwardNode = {
from(s"OtherMaster${name.getOrElse("")}") { inwardNode :*= TLBuffer(buffer) :*= gen }
}
def toTile(name: Option[String] = None)(gen: => TLNode): TLOutwardNode = {
to(s"Tile${name.getOrElse("")}") {
FlipRendering { implicit p =>
gen :*= delayNode :*= outwardNode
}
}
}
}
/** Provides buses that serve as attachment points,
* for use in traits that connect individual devices or external ports.
*/
trait HasPeripheryBus extends HasSystemBus {
private val pbusParams = p(PeripheryBusKey)
val pbusBeatBytes = pbusParams.beatBytes
val pbus = LazyModule(new PeripheryBus(pbusParams))
// The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
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pbus.fromSystemBus() { sbus.toPeripheryBus() { pbus.crossTLIn } }
}