2017-07-23 17:31:04 +02:00
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// See LICENSE.SiFive for license details.
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2018-01-12 21:29:27 +01:00
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package freechips.rocketchip.subsystem
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2017-07-23 17:31:04 +02:00
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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case class PeripheryBusParams(
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beatBytes: Int,
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blockBytes: Int,
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2017-07-25 09:55:55 +02:00
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frequency: BigInt = BigInt(100000000) // 100 MHz as default bus frequency
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2018-02-15 23:01:49 +01:00
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) extends HasTLBusParams
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2017-07-23 17:31:04 +02:00
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2017-09-09 03:33:44 +02:00
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case object PeripheryBusKey extends Field[PeripheryBusParams]
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2017-07-23 17:31:04 +02:00
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2018-02-15 23:01:49 +01:00
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class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCrossing = SynchronousCrossing())
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(implicit p: Parameters) extends TLBusWrapper(params, "PeripheryBus")
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with HasTLXbarPhy
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with HasCrossing {
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private def bufferTo(buffer: BufferParams): TLOutwardNode =
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TLBuffer(buffer) :*= delayNode :*= outwardNode
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private def fragmentTo(minSize: Int, maxSize: Int, buffer: BufferParams): TLOutwardNode =
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TLFragmenter(minSize, maxSize) :*= bufferTo(buffer)
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private def fixedWidthTo(buffer: BufferParams): TLOutwardNode =
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TLWidthWidget(params.beatBytes) :*= bufferTo(buffer)
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2017-08-08 02:30:24 +02:00
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2018-02-15 23:01:49 +01:00
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def toSlave(
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name: Option[String] = None,
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buffer: BufferParams = BufferParams.none)
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(gen: => TLNode): TLOutwardNode = {
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to(s"Slave${name.getOrElse("")}") { gen :*= bufferTo(buffer) }
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2017-07-23 17:31:04 +02:00
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}
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2018-02-15 23:01:49 +01:00
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def toVariableWidthSlave(
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name: Option[String] = None,
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buffer: BufferParams = BufferParams.none)
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(gen: => TLNode): TLOutwardNode = {
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to(s"Slave${name.getOrElse("")}") {
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gen :*= fragmentTo(params.beatBytes, params.blockBytes, buffer)
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}
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2017-07-23 17:31:04 +02:00
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}
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2018-02-15 23:01:49 +01:00
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def toFixedWidthSlave(
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name: Option[String] = None,
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buffer: BufferParams = BufferParams.none)
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(gen: => TLNode): TLOutwardNode = {
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to(s"Slave${name.getOrElse("")}") {
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gen :*= fixedWidthTo(buffer)
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}
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}
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def toFixedWidthSingleBeatSlave(
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widthBytes: Int,
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name: Option[String] = None,
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buffer: BufferParams = BufferParams.none)
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(gen: => TLNode): TLOutwardNode = {
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to(s"Slave${name.getOrElse("")}") {
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gen :*= TLFragmenter(widthBytes, params.blockBytes) :*= fixedWidthTo(buffer)
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}
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2017-07-23 17:31:04 +02:00
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}
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2017-10-23 18:39:01 +02:00
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2018-02-15 23:01:49 +01:00
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def toLargeBurstSlave(
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maxXferBytes: Int,
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name: Option[String] = None,
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buffer: BufferParams = BufferParams.none)
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(gen: => TLNode): TLOutwardNode = {
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to(s"Slave${name.getOrElse("")}") {
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gen :*= fragmentTo(params.beatBytes, maxXferBytes, buffer)
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}
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}
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def fromSystemBus(
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arithmetic: Boolean = true,
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buffer: BufferParams = BufferParams.default)
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(gen: => TLOutwardNode) {
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from("SystemBus") {
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(inwardNode
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:*= TLBuffer(buffer)
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:*= TLAtomicAutomata(arithmetic = arithmetic)
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:*= gen)
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}
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}
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def fromOtherMaster(
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name: Option[String] = None,
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buffer: BufferParams = BufferParams.none)
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(gen: => TLNode): TLInwardNode = {
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from(s"OtherMaster${name.getOrElse("")}") { inwardNode :*= TLBuffer(buffer) :*= gen }
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}
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def toTile(name: Option[String] = None)(gen: => TLNode): TLOutwardNode = {
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to(s"Tile${name.getOrElse("")}") {
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FlipRendering { implicit p =>
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gen :*= delayNode :*= outwardNode
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2017-10-23 18:39:01 +02:00
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}
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}
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}
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2017-07-23 17:31:04 +02:00
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}
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/** Provides buses that serve as attachment points,
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* for use in traits that connect individual devices or external ports.
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*/
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trait HasPeripheryBus extends HasSystemBus {
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2017-09-09 03:33:44 +02:00
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private val pbusParams = p(PeripheryBusKey)
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2017-07-23 17:31:04 +02:00
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val pbusBeatBytes = pbusParams.beatBytes
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2017-09-26 23:58:18 +02:00
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val pbus = LazyModule(new PeripheryBus(pbusParams))
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2017-07-23 17:31:04 +02:00
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// The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
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2018-02-15 23:01:49 +01:00
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pbus.fromSystemBus() { sbus.toPeripheryBus() { pbus.crossTLIn } }
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2017-07-23 17:31:04 +02:00
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}
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