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rocket-chip/uncore/src/main/scala/network.scala

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Scala
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package uncore
import Chisel._
import scala.collection.mutable.Stack
class PairedDataIO[M <: Data, D <: Data]()(m: => M, d: => D) extends Bundle {
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val meta = Decoupled(m)
val data = Decoupled(d)
override def clone = { new PairedDataIO()(m,d).asInstanceOf[this.type] }
}
class PairedArbiterIO[M <: Data, D <: Data](n: Int)(m: => M, d: => D) extends Bundle {
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val in = Vec.fill(n){new PairedDataIO()(m,d)}.flip
val out = new PairedDataIO()(m,d)
val meta_chosen = Bits(OUTPUT, log2Up(n))
val data_chosen = Bits(OUTPUT, log2Up(n))
override def clone = { new PairedArbiterIO(n)(m,d).asInstanceOf[this.type] }
}
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class PairedLockingRRArbiter[M <: Data, D <: Data](n: Int, count: Int, needsLock: Option[M => Bool] = None)(meta: => M, data: => D) extends Module {
require(isPow2(count))
val io = new PairedArbiterIO(n)(meta,data)
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val locked = if(count > 1) Reg(init=Bool(false)) else Bool(false)
val lockIdx = if(count > 1) Reg(init=UInt(n-1)) else UInt(n-1)
val grant = List.fill(n)(Bool())
val meta_chosen = Bits(width = log2Up(n))
val chosen_meta_has_data = needsLock.map(_(io.in(meta_chosen).meta.bits)).getOrElse(Bool(true))
val valid_meta_has_data = io.in(meta_chosen).meta.valid && chosen_meta_has_data
val grant_chosen_meta = !(locked && chosen_meta_has_data)
(0 until n).map(i => io.in(i).meta.ready := grant(i) && grant_chosen_meta && io.out.meta.ready)
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(0 until n).map(i => io.in(i).data.ready := Mux(locked, lockIdx === UInt(i), grant(i) && valid_meta_has_data) && io.out.data.ready)
io.out.meta.valid := io.in(meta_chosen).meta.valid && grant_chosen_meta
io.out.data.valid := Mux(locked, io.in(lockIdx).data.valid, io.in(meta_chosen).data.valid && valid_meta_has_data)
io.out.meta.bits := io.in(meta_chosen).meta.bits
io.out.data.bits := Mux(locked, io.in(lockIdx).data.bits, io.in(meta_chosen).data.bits)
io.meta_chosen := meta_chosen
io.data_chosen := Mux(locked, lockIdx, meta_chosen)
if(count > 1){
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val cnt = Reg(init=UInt(0, width = log2Up(count)))
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val cnt_next = cnt + UInt(1)
when(io.out.data.fire()){
cnt := cnt_next
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when(cnt_next === UInt(0)) {
locked := Bool(false)
}
}
when(io.out.meta.fire()) {
when(needsLock.map(_(io.out.meta.bits)).getOrElse(Bool(true))) {
when(!locked) {
locked := Bool(true)
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lockIdx := Vec(io.in.map{in => in.meta.fire()}).indexWhere{i: Bool => i}
}
}
}
}
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val last_grant = Reg(init=Bits(0, log2Up(n)))
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val ctrl = ArbiterCtrl((0 until n).map(i => io.in(i).meta.valid && UInt(i) > last_grant) ++ io.in.map(_.meta.valid))
(0 until n).map(i => grant(i) := ctrl(i) && UInt(i) > last_grant || ctrl(i + n))
var choose = Bits(n-1)
for (i <- n-2 to 0 by -1)
choose = Mux(io.in(i).meta.valid, Bits(i), choose)
for (i <- n-1 to 1 by -1)
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choose = Mux(io.in(i).meta.valid && UInt(i) > last_grant, Bits(i), choose)
meta_chosen := choose
when (io.out.meta.fire()) { last_grant := meta_chosen }
}
class PairedCrossbar[M <: Data, D <: Data](count: Int, needsLock: Option[PhysicalNetworkIO[M] => Bool] = None)(meta: => M, data: => D)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
val io = new Bundle {
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val in = Vec.fill(conf.nEndpoints){new PairedDataIO()(new PhysicalNetworkIO()(meta),new PhysicalNetworkIO()(data))}.flip
val out = Vec.fill(conf.nEndpoints){new PairedDataIO()(new PhysicalNetworkIO()(meta),new PhysicalNetworkIO()(data))}
}
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val metaRdyVecs = List.fill(conf.nEndpoints)(Vec.fill(conf.nEndpoints){Bool()})
val dataRdyVecs = List.fill(conf.nEndpoints)(Vec.fill(conf.nEndpoints){Bool()})
val rdyVecs = metaRdyVecs zip dataRdyVecs
io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => {
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val rrarb = Module(new PairedLockingRRArbiter(conf.nEndpoints, count, needsLock)(io.in(0).meta.bits.clone, io.in(0).data.bits.clone))
rrarb.io.in zip io.in zip rdys._1 zip rdys._2 map { case (((arb, in), meta_rdy), data_rdy) => {
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arb.meta.valid := in.meta.valid && (in.meta.bits.header.dst === UInt(i))
arb.meta.bits := in.meta.bits
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meta_rdy := arb.meta.ready && (in.meta.bits.header.dst === UInt(i))
arb.data.valid := in.data.valid && (in.data.bits.header.dst === UInt(i))
arb.data.bits := in.data.bits
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data_rdy := arb.data.ready && (in.data.bits.header.dst === UInt(i))
}}
out <> rrarb.io.out
}}
for(i <- 0 until conf.nEndpoints) {
io.in(i).meta.ready := rdyVecs.map(r => r._1(i)).reduceLeft(_||_)
io.in(i).data.ready := rdyVecs.map(r => r._2(i)).reduceLeft(_||_)
}
}
case class PhysicalNetworkConfiguration(nEndpoints: Int, idBits: Int)
class PhysicalHeader(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
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val src = UInt(width = conf.idBits)
val dst = UInt(width = conf.idBits)
}
class PhysicalNetworkIO[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
val header = (new PhysicalHeader)
val payload = data
override def clone = { new PhysicalNetworkIO()(data).asInstanceOf[this.type] }
}
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abstract class PhysicalNetwork(conf: PhysicalNetworkConfiguration) extends Module
class BasicCrossbar[T <: Data](count: Int = 1)(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
val io = new Bundle {
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val in = Vec.fill(conf.nEndpoints){Decoupled((new PhysicalNetworkIO){data})}.flip
val out = Vec.fill(conf.nEndpoints){Decoupled((new PhysicalNetworkIO){data})}
}
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val rdyVecs = List.fill(conf.nEndpoints)(Vec.fill(conf.nEndpoints)(Bool()))
io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => {
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val rrarb = Module(new LockingRRArbiter(io.in(0).bits, conf.nEndpoints, count))
(rrarb.io.in, io.in, rdys).zipped.map{ case (arb, in, rdy) => {
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arb.valid := in.valid && (in.bits.header.dst === UInt(i))
arb.bits := in.bits
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rdy := arb.ready && (in.bits.header.dst === UInt(i))
}}
out <> rrarb.io.out
}}
for(i <- 0 until conf.nEndpoints) {
io.in(i).ready := rdyVecs.map(r => r(i)).reduceLeft(_||_)
}
}
case class LogicalNetworkConfiguration(nEndpoints: Int, idBits: Int, nMasters: Int, nClients: Int)
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abstract class LogicalNetwork[TileLinkType <: Bundle](endpoints: Seq[CoherenceAgentRole])(implicit conf: LogicalNetworkConfiguration) extends Module {
override val io: Vec[TileLinkType]
val physicalNetworks: Seq[PhysicalNetwork]
require(endpoints.length == conf.nEndpoints)
}
class LogicalHeader(implicit conf: LogicalNetworkConfiguration) extends Bundle {
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val src = UInt(width = conf.idBits)
val dst = UInt(width = conf.idBits)
}
object FIFOedLogicalNetworkIOWrapper {
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def apply[T <: Data](in: DecoupledIO[T], src: UInt = UInt(0), dst: UInt = UInt(0))(implicit conf: LogicalNetworkConfiguration) = {
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val out = Decoupled((new LogicalNetworkIO){in.bits.clone}).asDirectionless
out.valid := in.valid
out.bits.payload := in.bits
out.bits.header.dst := dst
out.bits.header.src := src
in.ready := out.ready
out
}
}
object FIFOedLogicalNetworkIOUnwrapper {
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def apply[T <: Data](in: DecoupledIO[LogicalNetworkIO[T]])(implicit conf: LogicalNetworkConfiguration) = {
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val out = Decoupled(in.bits.payload.clone).asDirectionless
out.valid := in.valid
out.bits := in.bits.payload
in.ready := out.ready
out
}
}
class LogicalNetworkIO[T <: Data]()(data: => T)(implicit conf: LogicalNetworkConfiguration) extends Bundle {
val header = new LogicalHeader
val payload = data
override def clone = { new LogicalNetworkIO()(data).asInstanceOf[this.type] }
}