2013-07-25 08:22:36 +02:00
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package uncore
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import Chisel._
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import scala.collection.mutable.Stack
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class PairedDataIO[M <: Data, D <: Data]()(m: => M, d: => D) extends Bundle {
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2013-08-12 19:36:44 +02:00
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val meta = Decoupled(m)
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val data = Decoupled(d)
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2013-07-25 08:22:36 +02:00
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override def clone = { new PairedDataIO()(m,d).asInstanceOf[this.type] }
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}
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class PairedArbiterIO[M <: Data, D <: Data](n: Int)(m: => M, d: => D) extends Bundle {
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val in = Vec.fill(n){new PairedDataIO()(m,d)}.flip
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2013-07-25 08:22:36 +02:00
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val out = new PairedDataIO()(m,d)
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val meta_chosen = Bits(OUTPUT, log2Up(n))
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val data_chosen = Bits(OUTPUT, log2Up(n))
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override def clone = { new PairedArbiterIO(n)(m,d).asInstanceOf[this.type] }
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}
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2013-08-12 19:36:44 +02:00
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class PairedLockingRRArbiter[M <: Data, D <: Data](n: Int, count: Int, needsLock: Option[M => Bool] = None)(meta: => M, data: => D) extends Module {
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2013-07-25 08:22:36 +02:00
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require(isPow2(count))
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val io = new PairedArbiterIO(n)(meta,data)
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2013-08-12 19:36:44 +02:00
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val locked = if(count > 1) RegReset(Bool(false)) else Bool(false)
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val lockIdx = if(count > 1) RegReset(UInt(n-1)) else UInt(n-1)
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2013-07-25 08:22:36 +02:00
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val grant = List.fill(n)(Bool())
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val meta_chosen = Bits(width = log2Up(n))
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val chosen_meta_has_data = needsLock.map(_(io.in(meta_chosen).meta.bits)).getOrElse(Bool(true))
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val valid_meta_has_data = io.in(meta_chosen).meta.valid && chosen_meta_has_data
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val grant_chosen_meta = !(locked && chosen_meta_has_data)
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(0 until n).map(i => io.in(i).meta.ready := grant(i) && grant_chosen_meta && io.out.meta.ready)
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2013-08-12 19:36:44 +02:00
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(0 until n).map(i => io.in(i).data.ready := Mux(locked, lockIdx === UInt(i), grant(i) && valid_meta_has_data) && io.out.data.ready)
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2013-07-25 08:22:36 +02:00
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io.out.meta.valid := io.in(meta_chosen).meta.valid && grant_chosen_meta
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io.out.data.valid := Mux(locked, io.in(lockIdx).data.valid, io.in(meta_chosen).data.valid && valid_meta_has_data)
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io.out.meta.bits := io.in(meta_chosen).meta.bits
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io.out.data.bits := Mux(locked, io.in(lockIdx).data.bits, io.in(meta_chosen).data.bits)
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io.meta_chosen := meta_chosen
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io.data_chosen := Mux(locked, lockIdx, meta_chosen)
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if(count > 1){
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2013-08-12 19:36:44 +02:00
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val cnt = RegReset(UInt(0, width = log2Up(count)))
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val cnt_next = cnt + UInt(1)
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when(io.out.data.fire()){
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cnt := cnt_next
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when(cnt_next === UInt(0)) {
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locked := Bool(false)
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}
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}
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when(io.out.meta.fire()) {
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when(needsLock.map(_(io.out.meta.bits)).getOrElse(Bool(true))) {
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when(!locked) {
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locked := Bool(true)
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2013-08-12 19:36:44 +02:00
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lockIdx := Vec(io.in.map{in => in.meta.fire()}).indexWhere{i: Bool => i}
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2013-07-25 08:22:36 +02:00
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}
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}
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}
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}
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2013-08-12 19:36:44 +02:00
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val last_grant = RegReset(Bits(0, log2Up(n)))
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val ctrl = ArbiterCtrl((0 until n).map(i => io.in(i).meta.valid && UInt(i) > last_grant) ++ io.in.map(_.meta.valid))
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(0 until n).map(i => grant(i) := ctrl(i) && UInt(i) > last_grant || ctrl(i + n))
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var choose = Bits(n-1)
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for (i <- n-2 to 0 by -1)
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choose = Mux(io.in(i).meta.valid, Bits(i), choose)
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for (i <- n-1 to 1 by -1)
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choose = Mux(io.in(i).meta.valid && UInt(i) > last_grant, Bits(i), choose)
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meta_chosen := choose
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when (io.out.meta.fire()) { last_grant := meta_chosen }
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}
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class PairedCrossbar[M <: Data, D <: Data](count: Int, needsLock: Option[PhysicalNetworkIO[M] => Bool] = None)(meta: => M, data: => D)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
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val io = new Bundle {
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val in = Vec.fill(conf.nEndpoints){new PairedDataIO()(new PhysicalNetworkIO()(meta),new PhysicalNetworkIO()(data))}.flip
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val out = Vec.fill(conf.nEndpoints){new PairedDataIO()(new PhysicalNetworkIO()(meta),new PhysicalNetworkIO()(data))}
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2013-07-25 08:22:36 +02:00
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}
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2013-08-12 19:36:44 +02:00
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val metaRdyVecs = List.fill(conf.nEndpoints)(Vec.fill(conf.nEndpoints){Bool()})
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val dataRdyVecs = List.fill(conf.nEndpoints)(Vec.fill(conf.nEndpoints){Bool()})
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val rdyVecs = metaRdyVecs zip dataRdyVecs
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io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => {
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val rrarb = Module(new PairedLockingRRArbiter(conf.nEndpoints, count, needsLock)(io.in(0).meta.bits.clone, io.in(0).data.bits.clone))
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rrarb.io.in zip io.in zip rdys._1 zip rdys._2 map { case (((arb, in), meta_rdy), data_rdy) => {
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arb.meta.valid := in.meta.valid && (in.meta.bits.header.dst === UInt(i))
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arb.meta.bits := in.meta.bits
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meta_rdy := arb.meta.ready && (in.meta.bits.header.dst === UInt(i))
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arb.data.valid := in.data.valid && (in.data.bits.header.dst === UInt(i))
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arb.data.bits := in.data.bits
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data_rdy := arb.data.ready && (in.data.bits.header.dst === UInt(i))
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}}
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out <> rrarb.io.out
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}}
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for(i <- 0 until conf.nEndpoints) {
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io.in(i).meta.ready := rdyVecs.map(r => r._1(i)).reduceLeft(_||_)
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io.in(i).data.ready := rdyVecs.map(r => r._2(i)).reduceLeft(_||_)
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}
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}
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case class PhysicalNetworkConfiguration(nEndpoints: Int, idBits: Int)
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class PhysicalHeader(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
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val src = UInt(width = conf.idBits)
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val dst = UInt(width = conf.idBits)
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2013-07-25 08:22:36 +02:00
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}
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class PhysicalNetworkIO[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
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val header = (new PhysicalHeader)
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val payload = data
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override def clone = { new PhysicalNetworkIO()(data).asInstanceOf[this.type] }
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}
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2013-08-12 19:36:44 +02:00
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abstract class PhysicalNetwork(conf: PhysicalNetworkConfiguration) extends Module
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class BasicCrossbar[T <: Data](count: Int = 1)(data: => T)(implicit conf: PhysicalNetworkConfiguration) extends PhysicalNetwork(conf) {
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val io = new Bundle {
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val in = Vec.fill(conf.nEndpoints){Decoupled((new PhysicalNetworkIO){data})}.flip
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val out = Vec.fill(conf.nEndpoints){Decoupled((new PhysicalNetworkIO){data})}
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2013-07-25 08:22:36 +02:00
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}
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2013-08-12 19:36:44 +02:00
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val rdyVecs = List.fill(conf.nEndpoints)(Vec.fill(conf.nEndpoints)(Bool()))
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2013-07-25 08:22:36 +02:00
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io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => {
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val rrarb = Module(new LockingRRArbiter(io.in(0).bits, conf.nEndpoints, count))
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(rrarb.io.in, io.in, rdys).zipped.map{ case (arb, in, rdy) => {
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arb.valid := in.valid && (in.bits.header.dst === UInt(i))
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arb.bits := in.bits
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rdy := arb.ready && (in.bits.header.dst === UInt(i))
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}}
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out <> rrarb.io.out
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}}
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for(i <- 0 until conf.nEndpoints) {
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io.in(i).ready := rdyVecs.map(r => r(i)).reduceLeft(_||_)
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}
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}
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case class LogicalNetworkConfiguration(nEndpoints: Int, idBits: Int, nMasters: Int, nClients: Int)
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abstract class LogicalNetwork[TileLinkType <: Bundle](endpoints: Seq[CoherenceAgentRole])(implicit conf: LogicalNetworkConfiguration) extends Module {
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override val io: Vec[TileLinkType]
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val physicalNetworks: Seq[PhysicalNetwork]
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require(endpoints.length == conf.nEndpoints)
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}
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class LogicalHeader(implicit conf: LogicalNetworkConfiguration) extends Bundle {
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val src = UInt(width = conf.idBits)
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val dst = UInt(width = conf.idBits)
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}
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object FIFOedLogicalNetworkIOWrapper {
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def apply[T <: Data](in: DecoupledIO[T], src: UInt = UInt(0), dst: UInt = UInt(0))(implicit conf: LogicalNetworkConfiguration) = {
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val shim = Module((new FIFOedLogicalNetworkIOWrapper(src, dst)){ in.bits.clone })
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2013-07-25 08:22:36 +02:00
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shim.io.in.valid := in.valid
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shim.io.in.bits := in.bits
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in.ready := shim.io.in.ready
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shim.io.out
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}
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}
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class FIFOedLogicalNetworkIOWrapper[T <: Data](src: UInt, dst: UInt)(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Module {
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val io = new Bundle {
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val in = Decoupled(data).flip
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val out = Decoupled((new LogicalNetworkIO){data})
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2013-07-25 08:22:36 +02:00
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}
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io.out.valid := io.in.valid
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io.out.bits.payload := io.in.bits
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io.out.bits.header.dst := dst
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io.out.bits.header.src := src
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io.in.ready := io.out.ready
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}
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object FIFOedLogicalNetworkIOUnwrapper {
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def apply[T <: Data](in: DecoupledIO[LogicalNetworkIO[T]])(implicit conf: LogicalNetworkConfiguration) = {
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val shim = Module((new FIFOedLogicalNetworkIOUnwrapper){ in.bits.payload.clone })
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shim.io.in.valid := in.valid
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shim.io.in.bits := in.bits
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in.ready := shim.io.in.ready
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shim.io.out
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}
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}
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class FIFOedLogicalNetworkIOUnwrapper[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Module {
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val io = new Bundle {
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val in = Decoupled((new LogicalNetworkIO){data}).flip
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val out = Decoupled(data)
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2013-07-25 08:22:36 +02:00
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}
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io.out.valid := io.in.valid
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io.out.bits := io.in.bits.payload
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io.in.ready := io.out.ready
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}
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class LogicalNetworkIO[T <: Data]()(data: => T)(implicit conf: LogicalNetworkConfiguration) extends Bundle {
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val header = new LogicalHeader
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val payload = data
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override def clone = { new LogicalNetworkIO()(data).asInstanceOf[this.type] }
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}
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