2014-09-12 19:15:04 +02:00
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// See LICENSE for license details.
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2014-09-02 22:51:57 +02:00
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package rocketchip
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2014-08-23 10:26:03 +02:00
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import Chisel._
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import uncore._
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import rocket._
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import rocket.Util._
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2015-07-14 00:46:42 +02:00
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import zscale._
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2015-06-26 08:17:35 +02:00
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import scala.math.max
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2015-07-13 23:54:26 +02:00
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import DefaultTestSuites._
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2014-08-23 10:26:03 +02:00
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2014-10-06 22:43:40 +02:00
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class DefaultConfig extends ChiselConfig (
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topDefinitions = { (pname,site,here) =>
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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pname match {
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2015-07-14 00:46:42 +02:00
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//
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case UseZscale => false
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2014-10-06 22:43:40 +02:00
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//HTIF Parameters
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case HTIFWidth => Dump("HTIF_WIDTH", 16)
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case HTIFNSCR => 64
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case HTIFOffsetBits => site(CacheBlockOffsetBits)
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case HTIFNCores => site(NTiles)
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//Memory Parameters
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case PAddrBits => 32
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case PgIdxBits => 12
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case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
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case PgLevelBits => site(PgIdxBits) - log2Up(site(XLen)/8)
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case VPNBits => site(PgLevels) * site(PgLevelBits)
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case PPNBits => site(PAddrBits) - site(PgIdxBits)
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case VAddrBits => site(VPNBits) + site(PgIdxBits)
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case ASIdBits => 7
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case MIFTagBits => Dump("MEM_TAG_BITS",
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log2Up(site(NAcquireTransactors)+2) +
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log2Up(site(NBanksPerMemoryChannel)) +
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log2Up(site(NMemoryChannels)) + /* TODO: Remove for multichannel Top */
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1)
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case MIFDataBits => Dump("MEM_DATA_BITS", 128)
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case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
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case MIFDataBeats => site(TLDataBits)*site(TLDataBeats)/site(MIFDataBits)
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case NASTIDataBits => site(MIFDataBits)
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case NASTIAddrBits => site(MIFAddrBits)
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case NASTIIdBits => site(MIFTagBits)
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case UseNASTI => false
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2014-10-06 22:43:40 +02:00
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//Params used by all caches
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case NSets => findBy(CacheName)
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case NWays => findBy(CacheName)
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case RowBits => findBy(CacheName)
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case NTLBEntries => findBy(CacheName)
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case "L1I" => {
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case NSets => Knob("L1I_SETS") //64
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case NWays => Knob("L1I_WAYS") //4
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case RowBits => 4*site(CoreInstBits)
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case NTLBEntries => 8
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}:PF
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case "L1D" => {
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case NSets => Knob("L1D_SETS") //64
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case NWays => Knob("L1D_WAYS") //4
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case RowBits => 2*site(CoreDataBits)
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case NTLBEntries => 8
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}:PF
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case ECCCode => None
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case Replacer => () => new RandomReplacement(site(NWays))
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case AmoAluOperandBits => site(XLen)
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//L1InstCache
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case NBTBEntries => 62
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case NRAS => 2
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//L1DataCache
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case WordBits => site(XLen)
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case StoreDataQueueDepth => 17
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case ReplayQueueDepth => 16
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case NMSHRs => Knob("L1D_MSHRS")
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case LRSCCycles => 32
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//L2 Memory System Params
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case NAcquireTransactors => 7
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case L2StoreDataQueueDepth => 1
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case L2DirectoryRepresentation => new NullRepresentation(site(TLNCachingClients))
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case BuildL2CoherenceManager => () =>
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Module(new L2BroadcastHub, { case InnerTLId => "L1ToL2"; case OuterTLId => "L2ToMC" })
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//Tile Constants
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case BuildTiles => {
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TestGeneration.addSuites(rv64i.map(_("p")))
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TestGeneration.addSuites((if(site(UseVM)) List("pt","v") else List("pt")).flatMap(env => rv64u.map(_(env))))
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TestGeneration.addSuites(if(site(NTiles) > 1) List(mtBmarks, bmarks) else List(bmarks))
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List.fill(site(NTiles)){ (r:Bool) => Module(new RocketTile(resetSignal = r), {case TLId => "L1ToL2"}) }
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}
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case BuildRoCC => None
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case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
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case NPTWPorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 3)
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//Rocket Core Constants
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case FetchWidth => 1
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case RetireWidth => 1
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case UseVM => true
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case FastLoadWord => true
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case FastLoadByte => false
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case FastMulDiv => true
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case XLen => 64
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case NMultXpr => 32
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case BuildFPU => {
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val env = if(site(UseVM)) List("p","pt","v") else List("p","pt")
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if(site(FDivSqrt)) TestGeneration.addSuites(env.map(rv64uf))
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else TestGeneration.addSuites(env.map(rv64ufNoDiv))
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Some(() => Module(new FPU))
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}
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case FDivSqrt => true
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case SFMALatency => 2
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case DFMALatency => 3
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case CoreInstBits => 32
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case CoreDataBits => site(XLen)
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case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts))
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case NCustomMRWCSRs => 0
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//Uncore Paramters
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case LNEndpoints => site(TLNManagers) + site(TLNClients)
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case LNHeaderBits => log2Ceil(site(TLNManagers)) + log2Up(site(TLNClients))
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case TLBlockAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
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case TLNClients => site(TLNCachingClients) + site(TLNCachelessClients)
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case TLDataBits => site(CacheBlockBytes)*8/site(TLDataBeats)
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case TLDataBeats => 4
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case TLNetworkIsOrderedP2P => false
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case TLNManagers => findBy(TLId)
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case TLNCachingClients => findBy(TLId)
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case TLNCachelessClients => findBy(TLId)
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case TLCoherencePolicy => findBy(TLId)
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case TLMaxManagerXacts => findBy(TLId)
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case TLMaxClientXacts => findBy(TLId)
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case TLMaxClientsPerPort => findBy(TLId)
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case "L1ToL2" => {
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case TLNManagers => site(NBanksPerMemoryChannel)*site(NMemoryChannels)
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case TLNCachingClients => site(NTiles)
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case TLNCachelessClients => site(NTiles) + 1
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case TLCoherencePolicy => new MESICoherence(site(L2DirectoryRepresentation))
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case TLMaxManagerXacts => site(NAcquireTransactors) + 2
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case TLMaxClientXacts => max(site(NMSHRs),
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if(site(BuildRoCC).isEmpty) 1
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else site(RoCCMaxTaggedMemXacts))
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case TLMaxClientsPerPort => if(site(BuildRoCC).isEmpty) 1 else 3
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}:PF
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case "L2ToMC" => {
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case TLNManagers => 1
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case TLNCachingClients => site(NBanksPerMemoryChannel)
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case TLNCachelessClients => 0
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case TLCoherencePolicy => new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel)))
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case TLMaxManagerXacts => 1
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case TLMaxClientXacts => 1
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case TLMaxClientsPerPort => site(NAcquireTransactors) + 2
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}:PF
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case NTiles => Knob("NTILES")
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case NMemoryChannels => 1
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case NBanksPerMemoryChannel => Knob("NBANKS")
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case NOutstandingMemReqsPerChannel => site(NBanksPerMemoryChannel)*(site(NAcquireTransactors)+2)
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case BankIdLSB => 0
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case CacheBlockBytes => 64
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case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
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case UseBackupMemoryPort => true
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}},
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knobValues = {
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case "NTILES" => 1
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case "NBANKS" => 1
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case "L1D_MSHRS" => 2
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case "L1D_SETS" => 64
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case "L1D_WAYS" => 4
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case "L1I_SETS" => 64
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case "L1I_WAYS" => 4
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}
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)
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class DefaultVLSIConfig extends DefaultConfig
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class DefaultCPPConfig extends DefaultConfig
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2015-07-07 03:21:06 +02:00
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class With2Cores extends ChiselConfig(knobValues = { case "NTILES" => 2 })
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class With4Cores extends ChiselConfig(knobValues = { case "NTILES" => 4 })
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class With8Cores extends ChiselConfig(knobValues = { case "NTILES" => 8 })
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class With2Banks extends ChiselConfig(knobValues = { case "NBANKS" => 2 })
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class With4Banks extends ChiselConfig(knobValues = { case "NBANKS" => 4 })
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class With8Banks extends ChiselConfig(knobValues = { case "NBANKS" => 8 })
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class WithL2Cache extends ChiselConfig(
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(pname,site,here) => pname match {
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case "L2_CAPACITY_IN_KB" => Knob("L2_CAPACITY_IN_KB")
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case "L2Bank" => {
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case NSets => (((here[Int]("L2_CAPACITY_IN_KB")*1024) /
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site(CacheBlockBytes)) /
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site(NBanksPerMemoryChannel)*site(NMemoryChannels)) /
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site(NWays)
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case NWays => Knob("L2_WAYS")
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case RowBits => site(TLDataBits)
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}: PartialFunction[Any,Any]
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case NAcquireTransactors => 2
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case NSecondaryMisses => 4
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case L2DirectoryRepresentation => new FullRepresentation(site(TLNCachingClients))
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case BuildL2CoherenceManager => () =>
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Module(new L2HellaCacheBank, {
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case CacheName => "L2Bank"
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case InnerTLId => "L1ToL2"
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case OuterTLId => "L2ToMC"})
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},
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knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048 }
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)
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2015-07-07 03:21:06 +02:00
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class WithL2Capacity2048 extends ChiselConfig(knobValues = { case "L2_CAPACITY_IN_KB" => 2048 })
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class WithL2Capacity1024 extends ChiselConfig(knobValues = { case "L2_CAPACITY_IN_KB" => 1024 })
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class WithL2Capacity512 extends ChiselConfig(knobValues = { case "L2_CAPACITY_IN_KB" => 512 })
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class WithL2Capacity256 extends ChiselConfig(knobValues = { case "L2_CAPACITY_IN_KB" => 256 })
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class WithL2Capacity128 extends ChiselConfig(knobValues = { case "L2_CAPACITY_IN_KB" => 128 })
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class WithL2Capacity64 extends ChiselConfig(knobValues = { case "L2_CAPACITY_IN_KB" => 64 })
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2015-06-26 08:17:35 +02:00
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class DefaultL2Config extends ChiselConfig(new WithL2Cache ++ new DefaultConfig)
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class DefaultL2VLSIConfig extends ChiselConfig(new WithL2Cache ++ new DefaultVLSIConfig)
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class DefaultL2CPPConfig extends ChiselConfig(new WithL2Cache ++ new DefaultCPPConfig)
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class DefaultL2FPGAConfig extends ChiselConfig(new WithL2Capacity64 ++ new WithL2Cache ++ new DefaultFPGAConfig)
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2015-07-14 00:46:42 +02:00
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class WithZscale extends ChiselConfig(
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(pname,site,here) => pname match {
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case BuildZscale => {
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TestGeneration.addSuites(List(rv32ui("p"), rv32um("p")))
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(r: Bool) => Module(new Zscale(r), {case TLId => "L1ToL2"})
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}
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case UseZscale => true
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case BootROMCapacity => Dump("BOOT_CAPACITY", 16*1024)
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case DRAMCapacity => Dump("DRAM_CAPACITY", 64*1024*1024)
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2015-07-14 00:46:42 +02:00
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}
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)
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class ZscaleConfig extends ChiselConfig(new WithZscale ++ new DefaultConfig)
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2014-10-06 22:43:40 +02:00
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class FPGAConfig extends ChiselConfig (
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(pname,site,here) => pname match {
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case UseBackupMemoryPort => false
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}
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2014-10-06 22:43:40 +02:00
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)
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2014-09-24 02:05:14 +02:00
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2014-10-06 22:43:40 +02:00
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class DefaultFPGAConfig extends ChiselConfig(new FPGAConfig ++ new DefaultConfig)
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2014-10-07 11:05:10 +02:00
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class SmallConfig extends ChiselConfig (
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topDefinitions = { (pname,site,here) => pname match {
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case BuildFPU => None
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case FastMulDiv => false
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case NTLBEntries => 4
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case NBTBEntries => 8
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}},
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knobValues = {
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case "L1D_SETS" => 64
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case "L1D_WAYS" => 1
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2014-10-06 22:43:40 +02:00
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case "L1I_SETS" => 64
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case "L1I_WAYS" => 1
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2014-08-28 22:07:54 +02:00
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}
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2014-10-06 22:43:40 +02:00
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)
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2014-08-23 10:26:03 +02:00
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2014-10-07 11:05:10 +02:00
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class DefaultFPGASmallConfig extends ChiselConfig(new SmallConfig ++ new DefaultFPGAConfig)
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class ExampleSmallConfig extends ChiselConfig(new SmallConfig ++ new DefaultConfig)
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