74 lines
2.8 KiB
Scala
74 lines
2.8 KiB
Scala
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// See LICENSE.SiFive for license details.
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package uncore.tilelink2
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import config._
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import diplomacy._
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case class TLNodeNumbererNode(nodeAddressOffset: Option[Int] = None) extends TLCustomNode(0 to 999, 0 to 999)
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{
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val externalIn = true
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val externalOut = true
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def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
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require (oStars + iStars <= 1, s"${name} (a custom adapter) appears left of a :*= ${iStars} times and right of a :=* ${oStars} times; at most once is allowed${lazyModule.line}")
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if (oStars > 0) {
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require (iKnown >= oKnown, s"${name} (a custom adapter) has ${oKnown} outputs and ${iKnown} inputs; cannot assign ${iKnown-oKnown} edges to resolve :=*${lazyModule.line}")
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(0, iKnown - oKnown)
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} else {
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require (oKnown >= iKnown, s"${name} (a custom adapter) has ${oKnown} outputs and ${iKnown} inputs; cannot assign ${oKnown-iKnown} edges to resolve :*=${lazyModule.line}")
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(oKnown - iKnown, 0)
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}
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}
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def mapParamsD(n: Int, p: Seq[TLClientPortParameters]): Seq[TLClientPortParameters] = {
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require(n == p.size, s"${name} has ${p.size} inputs and ${n} outputs; they must match${lazyModule.line}")
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p
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}
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def mapParamsU(n: Int, p: Seq[TLManagerPortParameters]): Seq[TLManagerPortParameters] = {
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require(n == p.size, s"${name} has ${n} inputs and ${p.size} outputs; they must match${lazyModule.line}")
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val minNodeOffset = log2Ceil(p.map(_.maxAddress).max)
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val nodeOffset = nodeAddressOffset.getOrElse(minNodeOffset)
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require (nodeOffset >= minNodeOffset)
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p.zipWithIndex.map { case (mp, i) =>
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val nodeIndex = BigInt(i+1) << nodeOffset
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mp.copy(managers = mp.managers.map(m => m.copy(address = m.address.map(a => a.copy(base = a.base | nodeIndex)))))
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}
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}
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}
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class TLNodeNumberer(nodeAddressOffset: Option[Int] = None)(implicit p: Parameters) extends LazyModule
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{
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val node = TLNodeNumbererNode(nodeAddressOffset)
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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val minNodeOffset = log2Ceil(node.edgesOut.map(_.manager.maxAddress).max)
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val nodeOffset = nodeAddressOffset.getOrElse(minNodeOffset)
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(io.in zip io.out).zipWithIndex foreach { case ((in, out), i) =>
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out <> in
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// a&c address already get truncated
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in.b.bits.address := (UInt(i+1) << nodeOffset) | out.b.bits.address
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}
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}
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}
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object TLNodeNumberer
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{
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// applied to the TL source node; y.node := TLBuffer(x.node)
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def apply(nodeAddressOffset: Option[Int] = None)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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val numberer = LazyModule(new TLNodeNumberer(nodeAddressOffset))
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numberer.node := x
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numberer.node
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}
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}
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