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rocket-chip/src/main/scala/rocket/Breakpoint.scala

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Scala
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// See LICENSE.SiFive for license details.
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package rocket
import Chisel._
import Chisel.ImplicitConversions._
import config._
Heterogeneous Tiles (#550) Fundamental new features: * Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces. * Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile. * Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile. * Defined RocketCoreParams: All the parameters that can be varied per-core. * Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes. * Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created. * Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little. * Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support. Additional changes that got rolled in along the way: * rocket: Fix critical path through BTB for I$ index bits > pgIdxBits * coreplex: tiles connected via :=* * groundtest: updated to use TileParams * tilelink: cache cork requirements are relaxed to allow more cacheless masters
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import tile._
import util._
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class BPControl(implicit p: Parameters) extends CoreBundle()(p) {
val ttype = UInt(width = 4)
val dmode = Bool()
val maskmax = UInt(width = 6)
val reserved = UInt(width = xLen-24)
val action = Bool()
val chain = Bool()
val zero = UInt(width = 2)
val tmatch = UInt(width = 2)
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val m = Bool()
val h = Bool()
val s = Bool()
val u = Bool()
val x = Bool()
val w = Bool()
val r = Bool()
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def tType = 2
def maskMax = 4
def enabled(mstatus: MStatus) = !mstatus.debug && Cat(m, h, s, u)(mstatus.prv)
}
class BP(implicit p: Parameters) extends CoreBundle()(p) {
val control = new BPControl
val address = UInt(width = vaddrBits)
def mask(dummy: Int = 0) =
(0 until control.maskMax-1).scanLeft(control.tmatch(0))((m, i) => m && address(i)).asUInt
def pow2AddressMatch(x: UInt) =
(~x | mask()) === (~address | mask())
def rangeAddressMatch(x: UInt) =
(x >= address) ^ control.tmatch(0)
def addressMatch(x: UInt) =
Mux(control.tmatch(1), rangeAddressMatch(x), pow2AddressMatch(x))
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}
class BreakpointUnit(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val status = new MStatus().asInput
val bp = Vec(n, new BP).asInput
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val pc = UInt(INPUT, vaddrBits)
val ea = UInt(INPUT, vaddrBits)
val xcpt_if = Bool(OUTPUT)
val xcpt_ld = Bool(OUTPUT)
val xcpt_st = Bool(OUTPUT)
val debug_if = Bool(OUTPUT)
val debug_ld = Bool(OUTPUT)
val debug_st = Bool(OUTPUT)
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}
io.xcpt_if := false
io.xcpt_ld := false
io.xcpt_st := false
io.debug_if := false
io.debug_ld := false
io.debug_st := false
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io.bp.foldLeft((Bool(true), Bool(true), Bool(true))) { case ((ri, wi, xi), bp) =>
val en = bp.control.enabled(io.status)
val r = en && ri && bp.control.r && bp.addressMatch(io.ea)
val w = en && wi && bp.control.w && bp.addressMatch(io.ea)
val x = en && xi && bp.control.x && bp.addressMatch(io.pc)
val end = !bp.control.chain
when (end && r) { io.xcpt_ld := !bp.control.action; io.debug_ld := bp.control.action }
when (end && w) { io.xcpt_st := !bp.control.action; io.debug_st := bp.control.action }
when (end && x) { io.xcpt_if := !bp.control.action; io.debug_if := bp.control.action }
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(end || r, end || w, end || x)
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}
}